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403 lines
9.2 KiB
403 lines
9.2 KiB
/*
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* MPC8548 CDS Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8548CDS";
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compatible = "MPC8548CDS", "MPC85xxCDS";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8548@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <0>; // 33 MHz, from uboot
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bus-frequency = <0>; // 166 MHz
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clock-frequency = <0>; // 825 MHz, from uboot
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32-bit;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 08000000>; // 128M at 0x0
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};
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soc8548@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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ranges = <00001000 e0001000 000ff000
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80000000 80000000 10000000
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e2000000 e2000000 00800000
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90000000 90000000 10000000
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e2800000 e2800000 00800000
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a0000000 a0000000 20000000
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e3000000 e3000000 01000000>;
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reg = <e0000000 00001000>; // CCSRBAR
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bus-frequency = <0>;
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memory-controller@2000 {
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compatible = "fsl,8548-memory-controller";
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reg = <2000 1000>;
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interrupt-parent = <&mpic>;
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interrupts = <12 2>;
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};
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l2-cache-controller@20000 {
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compatible = "fsl,8548-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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interrupts = <10 2>;
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};
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <2b 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "mdio";
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compatible = "gianfar";
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reg = <24520 20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <24000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1d 2 1e 2 22 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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};
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ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <25000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <23 2 24 2 28 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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};
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/* eTSEC 3/4 are currently broken
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ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <26000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1f 2 20 2 21 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy2>;
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};
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ethernet@27000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <27000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <25 2 26 2 27 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy3>;
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};
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*/
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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serial@4600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities reg
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compatible = "fsl,mpc8548-guts";
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reg = <e0000 1000>;
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fsl,has-rstcr;
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};
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pci@8000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x4 (PCIX Slot 2) */
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02000 0 0 1 &mpic 0 1
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02000 0 0 2 &mpic 1 1
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02000 0 0 3 &mpic 2 1
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02000 0 0 4 &mpic 3 1
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/* IDSEL 0x5 (PCIX Slot 3) */
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02800 0 0 1 &mpic 1 1
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02800 0 0 2 &mpic 2 1
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02800 0 0 3 &mpic 3 1
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02800 0 0 4 &mpic 0 1
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/* IDSEL 0x6 (PCIX Slot 4) */
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03000 0 0 1 &mpic 2 1
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03000 0 0 2 &mpic 3 1
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03000 0 0 3 &mpic 0 1
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03000 0 0 4 &mpic 1 1
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/* IDSEL 0x8 (PCIX Slot 5) */
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04000 0 0 1 &mpic 0 1
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04000 0 0 2 &mpic 1 1
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04000 0 0 3 &mpic 2 1
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04000 0 0 4 &mpic 3 1
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/* IDSEL 0xC (Tsi310 bridge) */
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06000 0 0 1 &mpic 0 1
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06000 0 0 2 &mpic 1 1
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06000 0 0 3 &mpic 2 1
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06000 0 0 4 &mpic 3 1
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/* IDSEL 0x14 (Slot 2) */
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0a000 0 0 1 &mpic 0 1
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0a000 0 0 2 &mpic 1 1
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0a000 0 0 3 &mpic 2 1
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0a000 0 0 4 &mpic 3 1
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/* IDSEL 0x15 (Slot 3) */
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0a800 0 0 1 &mpic 1 1
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0a800 0 0 2 &mpic 2 1
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0a800 0 0 3 &mpic 3 1
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0a800 0 0 4 &mpic 0 1
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/* IDSEL 0x16 (Slot 4) */
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0b000 0 0 1 &mpic 2 1
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0b000 0 0 2 &mpic 3 1
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0b000 0 0 3 &mpic 0 1
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0b000 0 0 4 &mpic 1 1
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/* IDSEL 0x18 (Slot 5) */
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0c000 0 0 1 &mpic 0 1
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0c000 0 0 2 &mpic 1 1
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0c000 0 0 3 &mpic 2 1
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0c000 0 0 4 &mpic 3 1
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/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
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0E000 0 0 1 &mpic 0 1
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0E000 0 0 2 &mpic 1 1
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0E000 0 0 3 &mpic 2 1
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0E000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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bus-range = <0 0>;
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ranges = <02000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 e2000000 0 00800000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <8000 1000>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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pci_bridge@1c {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x00 (PrPMC Site) */
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0000 0 0 1 &mpic 0 1
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0000 0 0 2 &mpic 1 1
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0000 0 0 3 &mpic 2 1
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0000 0 0 4 &mpic 3 1
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/* IDSEL 0x04 (VIA chip) */
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2000 0 0 1 &mpic 0 1
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2000 0 0 2 &mpic 1 1
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2000 0 0 3 &mpic 2 1
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2000 0 0 4 &mpic 3 1
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/* IDSEL 0x05 (8139) */
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2800 0 0 1 &mpic 1 1
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/* IDSEL 0x06 (Slot 6) */
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3000 0 0 1 &mpic 2 1
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3000 0 0 2 &mpic 3 1
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3000 0 0 3 &mpic 0 1
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3000 0 0 4 &mpic 1 1
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/* IDESL 0x07 (Slot 7) */
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3800 0 0 1 &mpic 3 1
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3800 0 0 2 &mpic 0 1
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3800 0 0 3 &mpic 1 1
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3800 0 0 4 &mpic 2 1>;
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reg = <e000 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <02000000 0 80000000
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02000000 0 80000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00080000>;
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clock-frequency = <1fca055>;
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isa@4 {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <2000 0 0 0 0>;
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ranges = <1 0 01000000 0 0 00001000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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clock-frequency = <0>;
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interrupt-controller;
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device_type = "interrupt-controller";
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reg = <1 20 2
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1 a0 2
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1 4d0 2>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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built-in;
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compatible = "chrp,iic";
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interrupts = <0 1>;
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interrupt-parent = <&mpic>;
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};
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <1 70 2>;
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};
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};
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};
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};
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pci@9000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x15 */
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a800 0 0 1 &mpic b 1
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a800 0 0 2 &mpic 1 1
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a800 0 0 3 &mpic 2 1
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a800 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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bus-range = <0 0>;
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ranges = <02000000 0 90000000 90000000 0 10000000
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01000000 0 00000000 e2800000 0 00800000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <9000 1000>;
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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};
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/* PCI Express */
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pcie@a000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 (PEX) */
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00000 0 0 1 &mpic 0 1
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00000 0 0 2 &mpic 1 1
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00000 0 0 3 &mpic 2 1
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00000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <1a 2>;
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bus-range = <0 ff>;
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ranges = <02000000 0 a0000000 a0000000 0 20000000
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01000000 0 00000000 e3000000 0 08000000>;
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clock-frequency = <1fca055>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <a000 1000>;
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <40000 40000>;
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built-in;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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};
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};
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