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164 lines
3.9 KiB
164 lines
3.9 KiB
/******************************************************************************
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*
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* Copyright(c) 2009-2010 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL_92S_DM_H__
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#define __RTL_92S_DM_H__
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struct dig_t {
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u8 dig_enable_flag;
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u8 dig_algorithm;
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u8 dig_twoport_algorithm;
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u8 dig_ext_port_stage;
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u8 dig_dbgmode;
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u8 dig_slgorithm_switch;
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long rssi_lowthresh;
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long rssi_highthresh;
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u32 fa_lowthresh;
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u32 fa_highthresh;
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long rssi_highpower_lowthresh;
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long rssi_highpower_highthresh;
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u8 dig_state;
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u8 dig_highpwrstate;
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u8 cur_sta_connectstate;
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u8 pre_sta_connectstate;
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u8 cur_ap_connectstate;
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u8 pre_ap_connectstate;
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u8 cur_pd_thstate;
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u8 pre_pd_thstate;
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u8 cur_cs_ratiostate;
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u8 pre_cs_ratiostate;
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u32 pre_igvalue;
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u32 cur_igvalue;
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u8 backoff_enable_flag;
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char backoff_val;
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char backoffval_range_max;
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char backoffval_range_min;
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u8 rx_gain_range_max;
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u8 rx_gain_range_min;
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long rssi_val;
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};
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enum dm_dig_alg {
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DIG_ALGO_BY_FALSE_ALARM = 0,
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DIG_ALGO_BY_RSSI = 1,
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DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2,
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DIG_ALGO_BY_TOW_PORT = 3,
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DIG_ALGO_MAX
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};
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enum dm_dig_two_port_alg {
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DIG_TWO_PORT_ALGO_RSSI = 0,
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DIG_TWO_PORT_ALGO_FALSE_ALARM = 1,
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};
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enum dm_dig_dbg {
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DM_DBG_OFF = 0,
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DM_DBG_ON = 1,
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DM_DBG_MAX
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};
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enum dm_dig_sta {
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DM_STA_DIG_OFF = 0,
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DM_STA_DIG_ON,
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DM_STA_DIG_MAX
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};
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enum dm_dig_connect {
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DIG_STA_DISCONNECT = 0,
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DIG_STA_CONNECT = 1,
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DIG_STA_BEFORE_CONNECT = 2,
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DIG_AP_DISCONNECT = 3,
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DIG_AP_CONNECT = 4,
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DIG_AP_ADD_STATION = 5,
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DIG_CONNECT_MAX
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};
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enum dm_dig_ext_port_alg {
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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enum dm_ratr_sta {
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DM_RATR_STA_HIGH = 0,
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DM_RATR_STA_MIDDLEHIGH = 1,
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DM_RATR_STA_MIDDLE = 2,
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DM_RATR_STA_MIDDLELOW = 3,
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DM_RATR_STA_LOW = 4,
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DM_RATR_STA_ULTRALOW = 5,
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DM_RATR_STA_MAX
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};
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#define DM_TYPE_BYFW 0
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#define DM_TYPE_BYDRIVER 1
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#define TX_HIGH_PWR_LEVEL_NORMAL 0
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#define TX_HIGH_PWR_LEVEL_LEVEL1 1
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#define TX_HIGH_PWR_LEVEL_LEVEL2 2
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#define HAL_DM_DIG_DISABLE BIT(0) /* Disable Dig */
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#define HAL_DM_HIPWR_DISABLE BIT(1) /* Disable High Power */
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#define TX_HIGHPWR_LEVEL_NORMAL 0
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#define TX_HIGHPWR_LEVEL_NORMAL1 1
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#define TX_HIGHPWR_LEVEL_NORMAL2 2
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#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
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#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
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#define DM_DIG_THRESH_HIGH 40
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#define DM_DIG_THRESH_LOW 35
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#define DM_FALSEALARM_THRESH_LOW 40
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#define DM_FALSEALARM_THRESH_HIGH 1000
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#define DM_DIG_HIGH_PWR_THRESH_HIGH 75
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#define DM_DIG_HIGH_PWR_THRESH_LOW 70
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#define DM_DIG_BACKOFF 12
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#define DM_DIG_MAX 0x3e
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#define DM_DIG_MIN 0x1c
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#define DM_DIG_MIN_Netcore 0x12
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#define DM_DIG_BACKOFF_MAX 12
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#define DM_DIG_BACKOFF_MIN -4
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extern struct dig_t digtable;
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void rtl92s_dm_watchdog(struct ieee80211_hw *hw);
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void rtl92s_dm_init(struct ieee80211_hw *hw);
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void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw);
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#endif
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