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Hillf Danton b3ea581834 MIPS: Netlogic: Mark Netlogic chips as SMT capable ... Netlogic XLR chip has multiple cores. Each core includes four integrated hardware threads, and they share L1 data and instruction caches. If the chip is marked to be SMT capable, scheduler then could do more, say, idle load balancing. Changes are now confined only to the code of XLR, and hardware is probed to get core ID for correct setup. [jayachandranc: simplified and adapted for new merged XLR/XLP code] Signed-off-by: Hillf Danton <dhillf@gmail.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2972/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		13 years ago
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common	MIPS: Netlogic: Mark Netlogic chips as SMT capable	13 years ago
xlp	MIPS: Netlogic: Add support for XLP 3XX cores	13 years ago
xlr	MIPS: Netlogic: Merge some of XLR/XLP wakup code	13 years ago
Kconfig	MIPS: Netlogic: Use CPU_XLR instead of NLM_XLR	13 years ago
Makefile	MIPS: Netlogic: Add XLP makefiles and config	13 years ago
Platform	MIPS: Netlogic: Add XLP makefiles and config	13 years ago