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34 lines
1.1 KiB
34 lines
1.1 KiB
/*
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* Cache definitions for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef __ASM_CACHE_H
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#define __ASM_CACHE_H
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/* Bytes per L1 cache line */
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#define L1_CACHE_SHIFT (5)
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define __cacheline_aligned __aligned(L1_CACHE_BYTES)
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#define ____cacheline_aligned __aligned(L1_CACHE_BYTES)
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/* See http://kerneltrap.org/node/15100 */
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#define __read_mostly
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#endif
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