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114 lines
3.7 KiB
114 lines
3.7 KiB
/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __MACH_MXS_H__
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#define __MACH_MXS_H__
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#ifndef __ASSEMBLER__
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#include <linux/io.h>
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#endif
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#include <asm/mach-types.h>
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#include <mach/hardware.h>
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/*
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* MXS CPU types
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*/
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#define cpu_is_mx23() ( \
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machine_is_mx23evk() || \
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machine_is_stmp378x() || \
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0)
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#define cpu_is_mx28() ( \
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machine_is_mx28evk() || \
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machine_is_m28evk() || \
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machine_is_tx28() || \
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0)
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/*
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* IO addresses common to MXS-based
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*/
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#define MXS_IO_BASE_ADDR 0x80000000
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#define MXS_IO_SIZE SZ_1M
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#define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000)
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#define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000)
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#define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000)
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#define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000)
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#define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000)
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#define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000)
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#define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000)
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#define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000)
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#define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000)
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#define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000)
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#define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000)
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#define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000)
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#define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000)
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#define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000)
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#define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000)
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#define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000)
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#define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000)
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#define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000)
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#define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000)
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#define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000)
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#define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000)
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#define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000)
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#define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000)
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#define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000)
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/*
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* It maps the whole address space to [0xf4000000, 0xf50fffff].
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*
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* OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000
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* IO 0x80000000+0x100000 -> 0xf5000000+0x100000
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*/
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#define MXS_IO_P2V(x) (0xf4000000 + \
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(((x) & 0x80000000) >> 7) + \
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(((x) & 0x000fffff)))
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#define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x))
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#define mxs_map_entry(soc, name, _type) { \
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.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
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.pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
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.length = soc ## _ ## name ## _SIZE, \
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.type = _type, \
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}
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#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
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#define MXS_SET_ADDR 0x4
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#define MXS_CLR_ADDR 0x8
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#define MXS_TOG_ADDR 0xc
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#ifndef __ASSEMBLER__
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static inline void __mxs_setl(u32 mask, void __iomem *reg)
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{
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__raw_writel(mask, reg + MXS_SET_ADDR);
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}
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static inline void __mxs_clrl(u32 mask, void __iomem *reg)
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{
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__raw_writel(mask, reg + MXS_CLR_ADDR);
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}
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static inline void __mxs_togl(u32 mask, void __iomem *reg)
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{
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__raw_writel(mask, reg + MXS_TOG_ADDR);
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}
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#endif
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#endif /* __MACH_MXS_H__ */
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