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414 lines
12 KiB
414 lines
12 KiB
/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* Based on sun4i_backend.c, which is:
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* Copyright (C) 2015 Free Electrons
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* Copyright (C) 2015 NextThing Co
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <linux/component.h>
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#include <linux/dma-mapping.h>
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#include <linux/reset.h>
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#include <linux/of_device.h>
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#include "sun4i_drv.h"
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#include "sun8i_mixer.h"
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#include "sun8i_layer.h"
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#include "sunxi_engine.h"
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static void sun8i_mixer_commit(struct sunxi_engine *engine)
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{
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DRM_DEBUG_DRIVER("Committing changes\n");
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regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
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SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
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}
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void sun8i_mixer_layer_enable(struct sun8i_mixer *mixer,
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int layer, bool enable)
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{
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u32 val;
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/* Currently the first UI channel is used */
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int chan = mixer->cfg->vi_num;
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DRM_DEBUG_DRIVER("Enabling layer %d in channel %d\n", layer, chan);
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if (enable)
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val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
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else
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val = 0;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
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/* Set the alpha configuration */
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_DEF);
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_DEF);
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}
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static int sun8i_mixer_drm_format_to_layer(struct drm_plane *plane,
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u32 format, u32 *mode)
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{
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switch (format) {
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case DRM_FORMAT_ARGB8888:
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*mode = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_ARGB8888;
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break;
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case DRM_FORMAT_XRGB8888:
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*mode = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_XRGB8888;
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break;
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case DRM_FORMAT_RGB888:
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*mode = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_RGB888;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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int sun8i_mixer_update_layer_coord(struct sun8i_mixer *mixer,
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int layer, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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/* Currently the first UI channel is used */
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int chan = mixer->cfg->vi_num;
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DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
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if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
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DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
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state->crtc_w, state->crtc_h);
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regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE,
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SUN8I_MIXER_SIZE(state->crtc_w,
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state->crtc_h));
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DRM_DEBUG_DRIVER("Updating blender size\n");
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_INSIZE(0),
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SUN8I_MIXER_SIZE(state->crtc_w,
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state->crtc_h));
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_OUTSIZE,
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SUN8I_MIXER_SIZE(state->crtc_w,
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state->crtc_h));
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DRM_DEBUG_DRIVER("Updating channel size\n");
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_OVL_SIZE(chan),
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SUN8I_MIXER_SIZE(state->crtc_w,
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state->crtc_h));
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}
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/* Set the line width */
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DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_PITCH(chan, layer),
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fb->pitches[0]);
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/* Set height and width */
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DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
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state->crtc_w, state->crtc_h);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_SIZE(chan, layer),
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SUN8I_MIXER_SIZE(state->crtc_w, state->crtc_h));
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/* Set base coordinates */
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DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
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state->crtc_x, state->crtc_y);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_COORD(chan, layer),
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SUN8I_MIXER_COORD(state->crtc_x, state->crtc_y));
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return 0;
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}
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int sun8i_mixer_update_layer_formats(struct sun8i_mixer *mixer,
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int layer, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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bool interlaced = false;
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u32 val;
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/* Currently the first UI channel is used */
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int chan = mixer->cfg->vi_num;
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int ret;
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if (plane->state->crtc)
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interlaced = plane->state->crtc->state->adjusted_mode.flags
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& DRM_MODE_FLAG_INTERLACE;
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regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_OUTCTL,
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SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
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interlaced ?
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SUN8I_MIXER_BLEND_OUTCTL_INTERLACED : 0);
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DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
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interlaced ? "on" : "off");
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ret = sun8i_mixer_drm_format_to_layer(plane, fb->format->format,
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&val);
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if (ret) {
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DRM_DEBUG_DRIVER("Invalid format\n");
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return ret;
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}
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
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return 0;
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}
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int sun8i_mixer_update_layer_buffer(struct sun8i_mixer *mixer,
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int layer, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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struct drm_gem_cma_object *gem;
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dma_addr_t paddr;
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/* Currently the first UI channel is used */
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int chan = mixer->cfg->vi_num;
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int bpp;
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/* Get the physical address of the buffer in memory */
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gem = drm_fb_cma_get_gem_obj(fb, 0);
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DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
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/* Compute the start of the displayed memory */
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bpp = fb->format->cpp[0];
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paddr = gem->paddr + fb->offsets[0];
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/* Fixup framebuffer address for src coordinates */
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paddr += (state->src_x >> 16) * bpp;
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paddr += (state->src_y >> 16) * fb->pitches[0];
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/*
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* The hardware cannot correctly deal with negative crtc
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* coordinates, the display is cropped to the requested size,
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* but the display content is not moved.
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* Manually move the display content by fixup the framebuffer
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* address when crtc_x or crtc_y is negative, like what we
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* have did for src_x and src_y.
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*/
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if (state->crtc_x < 0)
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paddr += -state->crtc_x * bpp;
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if (state->crtc_y < 0)
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paddr += -state->crtc_y * fb->pitches[0];
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DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(chan, layer),
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lower_32_bits(paddr));
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return 0;
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}
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static const struct sunxi_engine_ops sun8i_engine_ops = {
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.commit = sun8i_mixer_commit,
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.layers_init = sun8i_layers_init,
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};
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static struct regmap_config sun8i_mixer_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0xbfffc, /* guessed */
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};
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static int sun8i_mixer_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct drm_device *drm = data;
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struct sun4i_drv *drv = drm->dev_private;
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struct sun8i_mixer *mixer;
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struct resource *res;
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void __iomem *regs;
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int i, ret;
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/*
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* The mixer uses single 32-bit register to store memory
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* addresses, so that it cannot deal with 64-bit memory
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* addresses.
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* Restrict the DMA mask so that the mixer won't be
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* allocated some memory that is too high.
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*/
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ret = dma_set_mask(dev, DMA_BIT_MASK(32));
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if (ret) {
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dev_err(dev, "Cannot do 32-bit DMA.\n");
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return ret;
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}
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mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
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if (!mixer)
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return -ENOMEM;
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dev_set_drvdata(dev, mixer);
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mixer->engine.ops = &sun8i_engine_ops;
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mixer->engine.node = dev->of_node;
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/* The ID of the mixer currently doesn't matter */
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mixer->engine.id = -1;
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mixer->cfg = of_device_get_match_data(dev);
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if (!mixer->cfg)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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mixer->engine.regs = devm_regmap_init_mmio(dev, regs,
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&sun8i_mixer_regmap_config);
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if (IS_ERR(mixer->engine.regs)) {
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dev_err(dev, "Couldn't create the mixer regmap\n");
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return PTR_ERR(mixer->engine.regs);
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}
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mixer->reset = devm_reset_control_get(dev, NULL);
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if (IS_ERR(mixer->reset)) {
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dev_err(dev, "Couldn't get our reset line\n");
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return PTR_ERR(mixer->reset);
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}
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ret = reset_control_deassert(mixer->reset);
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if (ret) {
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dev_err(dev, "Couldn't deassert our reset line\n");
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return ret;
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}
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mixer->bus_clk = devm_clk_get(dev, "bus");
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if (IS_ERR(mixer->bus_clk)) {
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dev_err(dev, "Couldn't get the mixer bus clock\n");
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ret = PTR_ERR(mixer->bus_clk);
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goto err_assert_reset;
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}
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clk_prepare_enable(mixer->bus_clk);
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mixer->mod_clk = devm_clk_get(dev, "mod");
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if (IS_ERR(mixer->mod_clk)) {
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dev_err(dev, "Couldn't get the mixer module clock\n");
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ret = PTR_ERR(mixer->mod_clk);
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goto err_disable_bus_clk;
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}
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clk_prepare_enable(mixer->mod_clk);
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list_add_tail(&mixer->engine.list, &drv->engine_list);
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/* Reset the registers */
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for (i = 0x0; i < 0x20000; i += 4)
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regmap_write(mixer->engine.regs, i, 0);
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/* Enable the mixer */
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regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
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SUN8I_MIXER_GLOBAL_CTL_RT_EN);
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/* Initialize blender */
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_FCOLOR_CTL,
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SUN8I_MIXER_BLEND_FCOLOR_CTL_DEF);
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PREMULTIPLY,
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SUN8I_MIXER_BLEND_PREMULTIPLY_DEF);
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR,
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SUN8I_MIXER_BLEND_BKCOLOR_DEF);
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(0),
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SUN8I_MIXER_BLEND_MODE_DEF);
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_CK_CTL,
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SUN8I_MIXER_BLEND_CK_CTL_DEF);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_FCOLOR(0),
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SUN8I_MIXER_BLEND_ATTR_FCOLOR_DEF);
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/* Select the first UI channel */
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DRM_DEBUG_DRIVER("Selecting channel %d (first UI channel)\n",
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mixer->cfg->vi_num);
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE,
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mixer->cfg->vi_num);
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return 0;
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err_disable_bus_clk:
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clk_disable_unprepare(mixer->bus_clk);
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err_assert_reset:
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reset_control_assert(mixer->reset);
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return ret;
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}
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static void sun8i_mixer_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct sun8i_mixer *mixer = dev_get_drvdata(dev);
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list_del(&mixer->engine.list);
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clk_disable_unprepare(mixer->mod_clk);
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clk_disable_unprepare(mixer->bus_clk);
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reset_control_assert(mixer->reset);
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}
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static const struct component_ops sun8i_mixer_ops = {
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.bind = sun8i_mixer_bind,
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.unbind = sun8i_mixer_unbind,
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};
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static int sun8i_mixer_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &sun8i_mixer_ops);
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}
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static int sun8i_mixer_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &sun8i_mixer_ops);
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return 0;
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}
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static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
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.vi_num = 2,
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.ui_num = 1,
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};
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static const struct of_device_id sun8i_mixer_of_table[] = {
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{
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.compatible = "allwinner,sun8i-v3s-de2-mixer",
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.data = &sun8i_v3s_mixer_cfg,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
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static struct platform_driver sun8i_mixer_platform_driver = {
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.probe = sun8i_mixer_probe,
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.remove = sun8i_mixer_remove,
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.driver = {
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.name = "sun8i-mixer",
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.of_match_table = sun8i_mixer_of_table,
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},
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};
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module_platform_driver(sun8i_mixer_platform_driver);
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MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
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MODULE_DESCRIPTION("Allwinner DE2 Mixer driver");
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MODULE_LICENSE("GPL");
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