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340 lines
8.2 KiB
340 lines
8.2 KiB
/*
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* STx GP3 board specific routines
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*
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* Dan Malek <dan@embeddededge.com>
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* Copyright 2004 Embedded Edge, LLC
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*
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* Copied from mpc8560_ads.c
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* Copyright 2002, 2003 Motorola Inc.
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*
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* Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2004-2005 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/blkdev.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/root_dev.h>
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#include <linux/seq_file.h>
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#include <linux/serial.h>
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#include <linux/initrd.h>
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#include <linux/module.h>
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#include <linux/fsl_devices.h>
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#include <linux/interrupt.h>
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#include <linux/rio.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/open_pic.h>
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#include <asm/bootinfo.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc85xx.h>
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#include <asm/irq.h>
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#include <asm/immap_85xx.h>
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#include <asm/cpm2.h>
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#include <asm/mpc85xx.h>
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#include <asm/ppc_sys.h>
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#include <syslib/cpm2_pic.h>
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#include <syslib/ppc85xx_common.h>
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#include <syslib/ppc85xx_rio.h>
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unsigned char __res[sizeof(bd_t)];
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#ifndef CONFIG_PCI
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unsigned long isa_io_base = 0;
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unsigned long isa_mem_base = 0;
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unsigned long pci_dram_offset = 0;
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#endif
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/* Internal interrupts are all Level Sensitive, and Positive Polarity */
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static u8 gp3_openpic_initsenses[] __initdata = {
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MPC85XX_INTERNAL_IRQ_SENSES,
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0x0, /* External 0: */
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#if defined(CONFIG_PCI)
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
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#else
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0x0, /* External 1: */
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0x0, /* External 2: */
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0x0, /* External 3: */
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0x0, /* External 4: */
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#endif
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0x0, /* External 5: */
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0x0, /* External 6: */
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0x0, /* External 7: */
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0x0, /* External 8: */
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0x0, /* External 9: */
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0x0, /* External 10: */
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0x0, /* External 11: */
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};
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/*
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* Setup the architecture
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*/
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static void __init
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gp3_setup_arch(void)
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{
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bd_t *binfo = (bd_t *) __res;
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unsigned int freq;
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struct gianfar_platform_data *pdata;
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struct gianfar_mdio_data *mdata;
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cpm2_reset();
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/* get the core frequency */
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freq = binfo->bi_intfreq;
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if (ppc_md.progress)
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ppc_md.progress("gp3_setup_arch()", 0);
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/* Set loops_per_jiffy to a half-way reasonable value,
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for use until calibrate_delay gets called. */
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loops_per_jiffy = freq / HZ;
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#ifdef CONFIG_PCI
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/* setup PCI host bridges */
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mpc85xx_setup_hose();
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#endif
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/* setup the board related info for the MDIO bus */
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mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
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mdata->irq[2] = MPC85xx_IRQ_EXT5;
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mdata->irq[4] = MPC85xx_IRQ_EXT5;
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mdata->irq[31] = PHY_POLL;
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/* setup the board related information for the enet controllers */
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pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
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if (pdata) {
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/* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
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pdata->bus_id = 0;
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pdata->phy_id = 2;
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memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
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}
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pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
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if (pdata) {
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/* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
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pdata->bus_id = 0;
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pdata->phy_id = 4;
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memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
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}
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
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}
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static irqreturn_t cpm2_cascade(int irq, void *dev_id)
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{
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while ((irq = cpm2_get_irq()) >= 0)
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__do_IRQ(irq);
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return IRQ_HANDLED;
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}
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static struct irqaction cpm2_irqaction = {
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.handler = cpm2_cascade,
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.flags = IRQF_DISABLED,
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.mask = CPU_MASK_NONE,
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.name = "cpm2_cascade",
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};
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static void __init
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gp3_init_IRQ(void)
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{
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bd_t *binfo = (bd_t *) __res;
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/*
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* Setup OpenPIC
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*/
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/* Determine the Physical Address of the OpenPIC regs */
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phys_addr_t OpenPIC_PAddr =
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binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
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OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
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OpenPIC_InitSenses = gp3_openpic_initsenses;
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OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
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/* Skip reserved space and internal sources */
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openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
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/* Map PIC IRQs 0-11 */
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openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
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/*
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* Let openpic interrupts starting from an offset, to
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* leave space for cascading interrupts underneath.
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*/
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openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
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/* Setup CPM2 PIC */
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cpm2_init_IRQ();
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setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
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return;
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}
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static int
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gp3_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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bd_t *binfo = (bd_t *) __res;
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uint memsize;
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unsigned int freq;
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extern unsigned long total_memory; /* in mm/init */
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/* get the core frequency */
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freq = binfo->bi_intfreq;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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memsize = total_memory;
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seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
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seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
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seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
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freq % 1000000);
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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/* Display the amount of memory */
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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return 0;
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}
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#ifdef CONFIG_PCI
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int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
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unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{PIRQA, PIRQB, PIRQC, PIRQD},
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{PIRQD, PIRQA, PIRQB, PIRQC},
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{PIRQC, PIRQD, PIRQA, PIRQB},
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{PIRQB, PIRQC, PIRQD, PIRQA},
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};
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const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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int mpc85xx_exclude_device(u_char bus, u_char devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_RAPIDIO
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void
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platform_rio_init(void)
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{
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/*
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* The STx firmware configures the RapidIO Local Access Window
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* at 0xc0000000 with a size of 512MB.
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*/
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mpc85xx_rio_setup(0xc0000000, 0x20000000);
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}
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#endif /* CONFIG_RAPIDIO */
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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/* parse_bootinfo must always be called first */
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parse_bootinfo(find_bootinfo());
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/*
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* If we were passed in a board information, copy it into the
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* residual data area.
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*/
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if (r3) {
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memcpy((void *) __res, (void *) (r3 + KERNELBASE),
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sizeof (bd_t));
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}
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#if defined(CONFIG_BLK_DEV_INITRD)
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/*
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* If the init RAM disk has been configured in, and there's a valid
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* starting address for it, set it up.
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*/
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if (r4) {
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initrd_start = r4 + KERNELBASE;
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initrd_end = r5 + KERNELBASE;
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}
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#endif /* CONFIG_BLK_DEV_INITRD */
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/* Copy the kernel command line arguments to a safe place. */
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if (r6) {
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*(char *) (r7 + KERNELBASE) = 0;
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strcpy(cmd_line, (char *) (r6 + KERNELBASE));
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}
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identify_ppc_sys_by_id(mfspr(SPRN_SVR));
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/* setup the PowerPC module struct */
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ppc_md.setup_arch = gp3_setup_arch;
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ppc_md.show_cpuinfo = gp3_show_cpuinfo;
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ppc_md.init_IRQ = gp3_init_IRQ;
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ppc_md.get_irq = openpic_get_irq;
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ppc_md.restart = mpc85xx_restart;
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ppc_md.power_off = mpc85xx_power_off;
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ppc_md.halt = mpc85xx_halt;
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ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
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ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
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if (ppc_md.progress)
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ppc_md.progress("platform_init(): exit", 0);
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return;
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}
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