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David S. Miller 56fb4df6da [SPARC64]: Elminate all usage of hard-coded trap globals. ... UltraSPARC has special sets of global registers which are switched to for certain trap types. There is one set for MMU related traps, one set of Interrupt Vector processing, and another set (called the Alternate globals) for all other trap types. For what seems like forever we've hard coded the values in some of these trap registers. Some examples include: 1) Interrupt Vector global %g6 holds current processors interrupt work struct where received interrupts are managed for IRQ handler dispatch. 2) MMU global %g7 holds the base of the page tables of the currently active address space. 3) Alternate global %g6 held the current_thread_info() value. Such hardcoding has resulted in some serious issues in many areas. There are some code sequences where having another register available would help clean up the implementation. Taking traps such as cross-calls from the OBP firmware requires some trick code sequences wherein we have to save away and restore all of the special sets of global registers when we enter/exit OBP. We were also using the IMMU TSB register on SMP to hold the per-cpu area base address, which doesn't work any longer now that we actually use the TSB facility of the cpu. The implementation is pretty straight forward. One tricky bit is getting the current processor ID as that is different on different cpu variants. We use a stub with a fancy calling convention which we patch at boot time. The calling convention is that the stub is branched to and the (PC - 4) to return to is in register %g1. The cpu number is left in %g6. This stub can be invoked by using the __GET_CPUID macro. We use an array of per-cpu trap state to store the current thread and physical address of the current address space's page tables. The TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this table, it uses __GET_CPUID and also clobbers %g1. TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load the current processor's IRQ software state into %g6. It also uses __GET_CPUID and clobbers %g1. Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the current address space's page tables into %g7, it clobbers %g1 and uses __GET_CPUID. Many refinements are possible, as well as some tuning, with this stuff in place. Signed-off-by: David S. Miller <davem@davemloft.net>		19 years ago
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alpha	[PATCH] alpha: fix IRQ handling lockup	19 years ago
arm	[ARM] 3362/1: [cleanup] - duplicate decleration of mem_fclk_21285	19 years ago
arm26	…
cris	…
frv	…
h8300	[PATCH] add missing pm_power_off's	19 years ago
i386	[PATCH] x86: check for online cpus before bringing them up	19 years ago
ia64	[IA64] Fix race in the accessed/dirty bit handlers	19 years ago
m32r	…
m68k	…
m68knommu	…
mips	[MIPS] SB1: Check for -mno-sched-prolog if building corelis debug kernel.	19 years ago
parisc	…
powerpc	powerpc: update defconfigs	19 years ago
ppc	powerpc: Fix various syscall/signal/swapcontext bugs	19 years ago
s390	[PATCH] s390: Increase spinlock retry code performance	19 years ago
sh	[PATCH] arch/sh/Kconfig: don't source non-existing Kconfig files	19 years ago
sh64	…
sparc	[SPARC]: BUG_ON() Conversion in arch/sparc/kernel/ioport.c	19 years ago
sparc64	[SPARC64]: Elminate all usage of hard-coded trap globals.	19 years ago
um	…
v850	[PATCH] add missing pm_power_off's	19 years ago
x86_64	Revert "[PATCH] x86-64: Fix up handling of non canonical user RIPs"	19 years ago
xtensa	[PATCH] xtensa must set RWSEM_GENERIC_SPINLOCK=y	19 years ago