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387 lines
8.9 KiB
387 lines
8.9 KiB
/*
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* linux/arch/arm/mach-omap2/pm.c
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*
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* OMAP2 Power Management Routines
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*
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* Copyright (C) 2006 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/suspend.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/interrupt.h>
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#include <linux/sysfs.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/atomic.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/mach-types.h>
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#include <asm/arch/irqs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sram.h>
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#include <asm/arch/pm.h>
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#include "prcm-regs.h"
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static struct clk *vclk;
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static void (*omap2_sram_idle)(void);
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static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
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static void (*saved_idle)(void);
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extern void __init pmdomain_init(void);
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extern void pmdomain_set_autoidle(void);
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static unsigned int omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_SIZE];
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void omap2_pm_idle(void)
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{
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local_irq_disable();
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local_fiq_disable();
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if (need_resched()) {
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local_fiq_enable();
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local_irq_enable();
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return;
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}
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/*
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* Since an interrupt may set up a timer, we don't want to
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* reprogram the hardware timer with interrupts enabled.
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* Re-enable interrupts only after returning from idle.
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*/
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timer_dyn_reprogram();
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omap2_sram_idle();
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local_fiq_enable();
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local_irq_enable();
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}
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static int omap2_pm_prepare(void)
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{
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/* We cannot sleep in idle until we have resumed */
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saved_idle = pm_idle;
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pm_idle = NULL;
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return 0;
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}
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#define INT0_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) | \
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OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) | \
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OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3))
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#define INT1_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4))
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#define INT2_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) | \
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OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) | \
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OMAP_IRQ_BIT(INT_24XX_UART3_IRQ))
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#define preg(reg) printk("%s\t(0x%p):\t0x%08x\n", #reg, ®, reg);
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static void omap2_pm_debug(char * desc)
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{
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printk("%s:\n", desc);
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preg(CM_CLKSTCTRL_MPU);
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preg(CM_CLKSTCTRL_CORE);
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preg(CM_CLKSTCTRL_GFX);
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preg(CM_CLKSTCTRL_DSP);
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preg(CM_CLKSTCTRL_MDM);
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preg(PM_PWSTCTRL_MPU);
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preg(PM_PWSTCTRL_CORE);
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preg(PM_PWSTCTRL_GFX);
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preg(PM_PWSTCTRL_DSP);
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preg(PM_PWSTCTRL_MDM);
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preg(PM_PWSTST_MPU);
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preg(PM_PWSTST_CORE);
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preg(PM_PWSTST_GFX);
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preg(PM_PWSTST_DSP);
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preg(PM_PWSTST_MDM);
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preg(CM_AUTOIDLE1_CORE);
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preg(CM_AUTOIDLE2_CORE);
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preg(CM_AUTOIDLE3_CORE);
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preg(CM_AUTOIDLE4_CORE);
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preg(CM_AUTOIDLE_WKUP);
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preg(CM_AUTOIDLE_PLL);
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preg(CM_AUTOIDLE_DSP);
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preg(CM_AUTOIDLE_MDM);
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preg(CM_ICLKEN1_CORE);
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preg(CM_ICLKEN2_CORE);
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preg(CM_ICLKEN3_CORE);
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preg(CM_ICLKEN4_CORE);
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preg(CM_ICLKEN_GFX);
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preg(CM_ICLKEN_WKUP);
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preg(CM_ICLKEN_DSP);
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preg(CM_ICLKEN_MDM);
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preg(CM_IDLEST1_CORE);
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preg(CM_IDLEST2_CORE);
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preg(CM_IDLEST3_CORE);
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preg(CM_IDLEST4_CORE);
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preg(CM_IDLEST_GFX);
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preg(CM_IDLEST_WKUP);
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preg(CM_IDLEST_CKGEN);
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preg(CM_IDLEST_DSP);
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preg(CM_IDLEST_MDM);
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preg(RM_RSTST_MPU);
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preg(RM_RSTST_GFX);
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preg(RM_RSTST_WKUP);
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preg(RM_RSTST_DSP);
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preg(RM_RSTST_MDM);
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preg(PM_WKDEP_MPU);
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preg(PM_WKDEP_CORE);
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preg(PM_WKDEP_GFX);
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preg(PM_WKDEP_DSP);
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preg(PM_WKDEP_MDM);
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preg(CM_FCLKEN_WKUP);
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preg(CM_ICLKEN_WKUP);
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preg(CM_IDLEST_WKUP);
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preg(CM_AUTOIDLE_WKUP);
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preg(CM_CLKSEL_WKUP);
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preg(PM_WKEN_WKUP);
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preg(PM_WKST_WKUP);
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}
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static inline void omap2_pm_save_registers(void)
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{
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/* Save interrupt registers */
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OMAP24XX_SAVE(INTC_MIR0);
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OMAP24XX_SAVE(INTC_MIR1);
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OMAP24XX_SAVE(INTC_MIR2);
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/* Save power control registers */
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OMAP24XX_SAVE(CM_CLKSTCTRL_MPU);
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OMAP24XX_SAVE(CM_CLKSTCTRL_CORE);
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OMAP24XX_SAVE(CM_CLKSTCTRL_GFX);
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OMAP24XX_SAVE(CM_CLKSTCTRL_DSP);
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OMAP24XX_SAVE(CM_CLKSTCTRL_MDM);
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/* Save power state registers */
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OMAP24XX_SAVE(PM_PWSTCTRL_MPU);
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OMAP24XX_SAVE(PM_PWSTCTRL_CORE);
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OMAP24XX_SAVE(PM_PWSTCTRL_GFX);
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OMAP24XX_SAVE(PM_PWSTCTRL_DSP);
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OMAP24XX_SAVE(PM_PWSTCTRL_MDM);
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/* Save autoidle registers */
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OMAP24XX_SAVE(CM_AUTOIDLE1_CORE);
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OMAP24XX_SAVE(CM_AUTOIDLE2_CORE);
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OMAP24XX_SAVE(CM_AUTOIDLE3_CORE);
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OMAP24XX_SAVE(CM_AUTOIDLE4_CORE);
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OMAP24XX_SAVE(CM_AUTOIDLE_WKUP);
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OMAP24XX_SAVE(CM_AUTOIDLE_PLL);
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OMAP24XX_SAVE(CM_AUTOIDLE_DSP);
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OMAP24XX_SAVE(CM_AUTOIDLE_MDM);
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/* Save idle state registers */
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OMAP24XX_SAVE(CM_IDLEST1_CORE);
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OMAP24XX_SAVE(CM_IDLEST2_CORE);
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OMAP24XX_SAVE(CM_IDLEST3_CORE);
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OMAP24XX_SAVE(CM_IDLEST4_CORE);
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OMAP24XX_SAVE(CM_IDLEST_GFX);
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OMAP24XX_SAVE(CM_IDLEST_WKUP);
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OMAP24XX_SAVE(CM_IDLEST_CKGEN);
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OMAP24XX_SAVE(CM_IDLEST_DSP);
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OMAP24XX_SAVE(CM_IDLEST_MDM);
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/* Save clock registers */
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OMAP24XX_SAVE(CM_FCLKEN1_CORE);
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OMAP24XX_SAVE(CM_FCLKEN2_CORE);
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OMAP24XX_SAVE(CM_ICLKEN1_CORE);
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OMAP24XX_SAVE(CM_ICLKEN2_CORE);
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OMAP24XX_SAVE(CM_ICLKEN3_CORE);
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OMAP24XX_SAVE(CM_ICLKEN4_CORE);
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}
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static inline void omap2_pm_restore_registers(void)
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{
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/* Restore clock state registers */
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OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU);
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OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE);
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OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX);
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OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP);
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OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM);
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/* Restore power state registers */
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OMAP24XX_RESTORE(PM_PWSTCTRL_MPU);
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OMAP24XX_RESTORE(PM_PWSTCTRL_CORE);
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OMAP24XX_RESTORE(PM_PWSTCTRL_GFX);
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OMAP24XX_RESTORE(PM_PWSTCTRL_DSP);
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OMAP24XX_RESTORE(PM_PWSTCTRL_MDM);
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/* Restore idle state registers */
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OMAP24XX_RESTORE(CM_IDLEST1_CORE);
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OMAP24XX_RESTORE(CM_IDLEST2_CORE);
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OMAP24XX_RESTORE(CM_IDLEST3_CORE);
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OMAP24XX_RESTORE(CM_IDLEST4_CORE);
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OMAP24XX_RESTORE(CM_IDLEST_GFX);
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OMAP24XX_RESTORE(CM_IDLEST_WKUP);
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OMAP24XX_RESTORE(CM_IDLEST_CKGEN);
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OMAP24XX_RESTORE(CM_IDLEST_DSP);
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OMAP24XX_RESTORE(CM_IDLEST_MDM);
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/* Restore autoidle registers */
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OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE);
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OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE);
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OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE);
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OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE);
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OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP);
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OMAP24XX_RESTORE(CM_AUTOIDLE_PLL);
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OMAP24XX_RESTORE(CM_AUTOIDLE_DSP);
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OMAP24XX_RESTORE(CM_AUTOIDLE_MDM);
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/* Restore clock registers */
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OMAP24XX_RESTORE(CM_FCLKEN1_CORE);
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OMAP24XX_RESTORE(CM_FCLKEN2_CORE);
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OMAP24XX_RESTORE(CM_ICLKEN1_CORE);
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OMAP24XX_RESTORE(CM_ICLKEN2_CORE);
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OMAP24XX_RESTORE(CM_ICLKEN3_CORE);
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OMAP24XX_RESTORE(CM_ICLKEN4_CORE);
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/* REVISIT: Clear interrupts here */
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/* Restore interrupt registers */
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OMAP24XX_RESTORE(INTC_MIR0);
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OMAP24XX_RESTORE(INTC_MIR1);
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OMAP24XX_RESTORE(INTC_MIR2);
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}
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static int omap2_pm_suspend(void)
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{
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int processor_type = 0;
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/* REVISIT: 0x21 or 0x26? */
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if (cpu_is_omap2420())
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processor_type = 0x21;
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if (!processor_type)
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return -ENOTSUPP;
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local_irq_disable();
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local_fiq_disable();
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omap2_pm_save_registers();
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/* Disable interrupts except for the wake events */
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INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
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INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
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INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;
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pmdomain_set_autoidle();
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/* Clear old wake-up events */
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PM_WKST1_CORE = 0;
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PM_WKST2_CORE = 0;
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PM_WKST_WKUP = 0;
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/* Enable wake-up events */
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PM_WKEN1_CORE = (1 << 22) | (1 << 21); /* UART1 & 2 */
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PM_WKEN2_CORE = (1 << 2); /* UART3 */
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PM_WKEN_WKUP = (1 << 2) | (1 << 0); /* GPIO & GPT1 */
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/* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
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* in the SRAM suspend code */
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CM_FCLKEN1_CORE = 0;
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CM_FCLKEN2_CORE = 0;
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CM_ICLKEN1_CORE = 0;
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CM_ICLKEN3_CORE = 0;
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CM_ICLKEN4_CORE = 0;
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omap2_pm_debug("Status before suspend");
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/* Must wait for serial buffers to clear */
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mdelay(200);
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/* Jump to SRAM suspend code
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* REVISIT: When is this SDRC_DLLB_CTRL?
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*/
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omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);
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/* Back from sleep */
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omap2_pm_restore_registers();
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local_fiq_enable();
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local_irq_enable();
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return 0;
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}
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static int omap2_pm_enter(suspend_state_t state)
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{
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int ret = 0;
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switch (state)
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{
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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ret = omap2_pm_suspend();
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static void omap2_pm_finish(void)
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{
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pm_idle = saved_idle;
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}
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static struct platform_suspend_ops omap_pm_ops = {
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.prepare = omap2_pm_prepare,
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.enter = omap2_pm_enter,
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.finish = omap2_pm_finish,
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.valid = suspend_valid_only_mem,
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};
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int __init omap2_pm_init(void)
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{
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printk("Power Management for TI OMAP.\n");
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vclk = clk_get(NULL, "virt_prcm_set");
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if (IS_ERR(vclk)) {
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printk(KERN_ERR "Could not get PM vclk\n");
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return -ENODEV;
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}
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/*
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* We copy the assembler sleep/wakeup routines to SRAM.
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* These routines need to be in SRAM as that's the only
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* memory the MPU can see when it wakes up.
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*/
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omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
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omap24xx_idle_loop_suspend_sz);
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omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
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omap24xx_cpu_suspend_sz);
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suspend_set_ops(&omap_pm_ops);
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pm_idle = omap2_pm_idle;
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pmdomain_init();
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return 0;
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}
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__initcall(omap2_pm_init);
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