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62 lines
1.6 KiB
62 lines
1.6 KiB
/* Linker script for the FPGA implementation of the V850E2 NA85E2C cpu core
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(CONFIG_V850E2_FPGA85E2C). */
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MEMORY {
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/* Reset vector. */
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RESET : ORIGIN = 0, LENGTH = 0x10
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/* Interrupt vectors. */
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INTV : ORIGIN = 0x10, LENGTH = 0x470
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/* The `window' in RAM were we're allowed to load stuff. */
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RAM_LOW : ORIGIN = 0x480, LENGTH = 0x0005FB80
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/* Some more ram above the window were we can put bss &c. */
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RAM_HIGH : ORIGIN = 0x00060000, LENGTH = 0x000A0000
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/* This is the area visible from the outside world (we can use
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this only for uninitialized data). */
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VISIBLE : ORIGIN = 0x00200000, LENGTH = 0x00060000
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}
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SECTIONS {
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.reset : {
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__kram_start = . ;
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__intv_start = . ;
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*(.intv.reset) /* Reset vector */
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} > RESET
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.ram_low : {
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__r0_ram = . ; /* Must be near address 0. */
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. = . + 32 ;
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TEXT_CONTENTS
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DATA_CONTENTS
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ROOT_FS_CONTENTS
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RAMK_INIT_CONTENTS_NO_END
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INITRAMFS_CONTENTS
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} > RAM_LOW
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/* Where the interrupt vectors are initially loaded. */
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__intv_load_start = . ;
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.intv : {
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*(.intv.common) /* Vectors common to all v850e proc. */
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*(.intv.mach) /* Machine-specific int. vectors. */
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__intv_end = . ;
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} > INTV AT> RAM_LOW
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.ram_high : {
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/* This is here so that when we free init memory the
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load-time copy of the interrupt vectors and any empty
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space at the end of the `RAM_LOW' area is freed too. */
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. = ALIGN (4096);
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__init_end = . ;
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BSS_CONTENTS
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__kram_end = . ;
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BOOTMAP_CONTENTS
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} > RAM_HIGH
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.visible : {
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_memcons_output = . ;
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. = . + 0x8000 ;
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_memcons_output_end = . ;
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} > VISIBLE
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}
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