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61 lines
1.5 KiB
61 lines
1.5 KiB
/*
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* Clock control driver for Freescale STMP37XX/STMP378X - internal header file
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*
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* Author: Vitaly Wool <vital@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
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#define __ARCH_ARM_STMX3XXX_CLOCK_H__
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#ifndef __ASSEMBLER__
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struct clk_ops {
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int (*enable) (struct clk *);
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int (*disable) (struct clk *);
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long (*get_rate) (struct clk *);
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long (*round_rate) (struct clk *, u32);
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int (*set_rate) (struct clk *, u32);
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int (*set_parent) (struct clk *, struct clk *);
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};
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struct clk {
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struct clk *parent;
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u32 rate;
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u32 flags;
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u8 scale_shift;
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u8 enable_shift;
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u8 bypass_shift;
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u8 busy_bit;
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s8 usage;
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int enable_wait;
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int enable_negate;
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u32 saved_div;
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void __iomem *enable_reg;
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void __iomem *scale_reg;
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void __iomem *bypass_reg;
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void __iomem *busy_reg;
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struct clk_ops *ops;
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};
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#endif /* __ASSEMBLER__ */
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/* Flags */
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#define RATE_PROPAGATES (1<<0)
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#define NEEDS_INITIALIZATION (1<<1)
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#define PARENT_SET_RATE (1<<2)
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#define FIXED_RATE (1<<3)
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#define ENABLED (1<<4)
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#define NEEDS_SET_PARENT (1<<5)
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#endif
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