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729 lines
18 KiB
729 lines
18 KiB
/*
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* arch/arm/mach-orion5x/common.c
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*
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* Core functions for Marvell Orion 5x SoCs
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/mbus.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/mv643xx_i2c.h>
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#include <linux/ata_platform.h>
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#include <linux/spi/orion_spi.h>
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#include <net/dsa.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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#include <asm/timex.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/hardware.h>
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#include <mach/orion5x.h>
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#include <plat/ehci-orion.h>
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#include <plat/mv_xor.h>
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#include <plat/orion_nand.h>
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#include <plat/orion_wdt.h>
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#include <plat/time.h>
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#include "common.h"
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc orion5x_io_desc[] __initdata = {
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{
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.virtual = ORION5X_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
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.length = ORION5X_REGS_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = ORION5X_PCIE_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
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.length = ORION5X_PCIE_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = ORION5X_PCI_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
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.length = ORION5X_PCI_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = ORION5X_PCIE_WA_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
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.length = ORION5X_PCIE_WA_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init orion5x_map_io(void)
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{
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iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
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}
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/*****************************************************************************
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* EHCI
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****************************************************************************/
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static struct orion_ehci_data orion5x_ehci_data = {
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.dram = &orion5x_mbus_dram_info,
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.phy_version = EHCI_PHY_ORION,
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};
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static u64 ehci_dmamask = 0xffffffffUL;
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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static struct resource orion5x_ehci0_resources[] = {
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{
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.start = ORION5X_USB0_PHYS_BASE,
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.end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_ORION5X_USB0_CTRL,
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.end = IRQ_ORION5X_USB0_CTRL,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device orion5x_ehci0 = {
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.name = "orion-ehci",
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.id = 0,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &orion5x_ehci_data,
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},
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.resource = orion5x_ehci0_resources,
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.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
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};
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void __init orion5x_ehci0_init(void)
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{
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platform_device_register(&orion5x_ehci0);
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}
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/*****************************************************************************
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* EHCI1
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****************************************************************************/
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static struct resource orion5x_ehci1_resources[] = {
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{
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.start = ORION5X_USB1_PHYS_BASE,
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.end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_ORION5X_USB1_CTRL,
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.end = IRQ_ORION5X_USB1_CTRL,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device orion5x_ehci1 = {
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.name = "orion-ehci",
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.id = 1,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &orion5x_ehci_data,
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},
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.resource = orion5x_ehci1_resources,
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.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
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};
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void __init orion5x_ehci1_init(void)
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{
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platform_device_register(&orion5x_ehci1);
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}
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/*****************************************************************************
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* GigE
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
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.dram = &orion5x_mbus_dram_info,
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};
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static struct resource orion5x_eth_shared_resources[] = {
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{
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.start = ORION5X_ETH_PHYS_BASE + 0x2000,
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.end = ORION5X_ETH_PHYS_BASE + 0x3fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_ORION5X_ETH_ERR,
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.end = IRQ_ORION5X_ETH_ERR,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device orion5x_eth_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 0,
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.dev = {
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.platform_data = &orion5x_eth_shared_data,
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},
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.num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
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.resource = orion5x_eth_shared_resources,
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};
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static struct resource orion5x_eth_resources[] = {
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{
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.name = "eth irq",
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.start = IRQ_ORION5X_ETH_SUM,
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.end = IRQ_ORION5X_ETH_SUM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device orion5x_eth = {
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.name = MV643XX_ETH_NAME,
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.id = 0,
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.num_resources = 1,
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.resource = orion5x_eth_resources,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
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{
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eth_data->shared = &orion5x_eth_shared;
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orion5x_eth.dev.platform_data = eth_data;
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platform_device_register(&orion5x_eth_shared);
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platform_device_register(&orion5x_eth);
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}
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/*****************************************************************************
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* Ethernet switch
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****************************************************************************/
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static struct resource orion5x_switch_resources[] = {
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{
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device orion5x_switch_device = {
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.name = "dsa",
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.id = 0,
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.num_resources = 0,
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.resource = orion5x_switch_resources,
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};
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void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
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{
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int i;
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if (irq != NO_IRQ) {
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orion5x_switch_resources[0].start = irq;
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orion5x_switch_resources[0].end = irq;
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orion5x_switch_device.num_resources = 1;
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}
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d->netdev = &orion5x_eth.dev;
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for (i = 0; i < d->nr_chips; i++)
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d->chip[i].mii_bus = &orion5x_eth_shared.dev;
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orion5x_switch_device.dev.platform_data = d;
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platform_device_register(&orion5x_switch_device);
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}
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/*****************************************************************************
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* I2C
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****************************************************************************/
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static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
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.freq_m = 8, /* assumes 166 MHz TCLK */
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.freq_n = 3,
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.timeout = 1000, /* Default timeout of 1 second */
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};
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static struct resource orion5x_i2c_resources[] = {
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{
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.start = I2C_PHYS_BASE,
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.end = I2C_PHYS_BASE + 0x1f,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_ORION5X_I2C,
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.end = IRQ_ORION5X_I2C,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device orion5x_i2c = {
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.name = MV64XXX_I2C_CTLR_NAME,
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.id = 0,
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.num_resources = ARRAY_SIZE(orion5x_i2c_resources),
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.resource = orion5x_i2c_resources,
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.dev = {
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.platform_data = &orion5x_i2c_pdata,
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},
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};
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void __init orion5x_i2c_init(void)
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{
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platform_device_register(&orion5x_i2c);
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}
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/*****************************************************************************
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* SATA
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****************************************************************************/
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static struct resource orion5x_sata_resources[] = {
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{
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.name = "sata base",
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.start = ORION5X_SATA_PHYS_BASE,
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.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "sata irq",
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.start = IRQ_ORION5X_SATA,
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.end = IRQ_ORION5X_SATA,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device orion5x_sata = {
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.name = "sata_mv",
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.id = 0,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(orion5x_sata_resources),
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.resource = orion5x_sata_resources,
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};
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void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
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{
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sata_data->dram = &orion5x_mbus_dram_info;
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orion5x_sata.dev.platform_data = sata_data;
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platform_device_register(&orion5x_sata);
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}
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/*****************************************************************************
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* SPI
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****************************************************************************/
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static struct orion_spi_info orion5x_spi_plat_data = {
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.tclk = 0,
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.enable_clock_fix = 1,
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};
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static struct resource orion5x_spi_resources[] = {
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{
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.name = "spi base",
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.start = SPI_PHYS_BASE,
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.end = SPI_PHYS_BASE + 0x1f,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device orion5x_spi = {
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.name = "orion_spi",
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.id = 0,
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.dev = {
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.platform_data = &orion5x_spi_plat_data,
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},
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.num_resources = ARRAY_SIZE(orion5x_spi_resources),
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.resource = orion5x_spi_resources,
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};
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void __init orion5x_spi_init()
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{
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platform_device_register(&orion5x_spi);
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}
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/*****************************************************************************
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* UART0
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****************************************************************************/
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static struct plat_serial8250_port orion5x_uart0_data[] = {
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{
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.mapbase = UART0_PHYS_BASE,
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.membase = (char *)UART0_VIRT_BASE,
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.irq = IRQ_ORION5X_UART0,
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.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = 0,
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}, {
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},
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};
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static struct resource orion5x_uart0_resources[] = {
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{
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.start = UART0_PHYS_BASE,
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.end = UART0_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_ORION5X_UART0,
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.end = IRQ_ORION5X_UART0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device orion5x_uart0 = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = orion5x_uart0_data,
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},
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.resource = orion5x_uart0_resources,
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.num_resources = ARRAY_SIZE(orion5x_uart0_resources),
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};
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void __init orion5x_uart0_init(void)
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{
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platform_device_register(&orion5x_uart0);
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}
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/*****************************************************************************
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* UART1
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****************************************************************************/
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static struct plat_serial8250_port orion5x_uart1_data[] = {
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{
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.mapbase = UART1_PHYS_BASE,
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.membase = (char *)UART1_VIRT_BASE,
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.irq = IRQ_ORION5X_UART1,
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.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = 0,
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}, {
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},
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};
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static struct resource orion5x_uart1_resources[] = {
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{
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.start = UART1_PHYS_BASE,
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.end = UART1_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_ORION5X_UART1,
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.end = IRQ_ORION5X_UART1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device orion5x_uart1 = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM1,
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.dev = {
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.platform_data = orion5x_uart1_data,
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},
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.resource = orion5x_uart1_resources,
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.num_resources = ARRAY_SIZE(orion5x_uart1_resources),
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};
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void __init orion5x_uart1_init(void)
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{
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platform_device_register(&orion5x_uart1);
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}
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/*****************************************************************************
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* XOR engine
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****************************************************************************/
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struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
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.dram = &orion5x_mbus_dram_info,
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};
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static struct resource orion5x_xor_shared_resources[] = {
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{
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.name = "xor low",
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.start = ORION5X_XOR_PHYS_BASE,
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.end = ORION5X_XOR_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "xor high",
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.start = ORION5X_XOR_PHYS_BASE + 0x200,
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.end = ORION5X_XOR_PHYS_BASE + 0x2ff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device orion5x_xor_shared = {
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.name = MV_XOR_SHARED_NAME,
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.id = 0,
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.dev = {
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.platform_data = &orion5x_xor_shared_data,
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},
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.num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
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.resource = orion5x_xor_shared_resources,
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};
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static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
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static struct resource orion5x_xor0_resources[] = {
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[0] = {
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.start = IRQ_ORION5X_XOR0,
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.end = IRQ_ORION5X_XOR0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct mv_xor_platform_data orion5x_xor0_data = {
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.shared = &orion5x_xor_shared,
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.hw_id = 0,
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.pool_size = PAGE_SIZE,
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};
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static struct platform_device orion5x_xor0_channel = {
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.name = MV_XOR_NAME,
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.id = 0,
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.num_resources = ARRAY_SIZE(orion5x_xor0_resources),
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.resource = orion5x_xor0_resources,
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.dev = {
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.dma_mask = &orion5x_xor_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(64),
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.platform_data = (void *)&orion5x_xor0_data,
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},
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};
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static struct resource orion5x_xor1_resources[] = {
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[0] = {
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.start = IRQ_ORION5X_XOR1,
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.end = IRQ_ORION5X_XOR1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct mv_xor_platform_data orion5x_xor1_data = {
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.shared = &orion5x_xor_shared,
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.hw_id = 1,
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.pool_size = PAGE_SIZE,
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};
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static struct platform_device orion5x_xor1_channel = {
|
|
.name = MV_XOR_NAME,
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(orion5x_xor1_resources),
|
|
.resource = orion5x_xor1_resources,
|
|
.dev = {
|
|
.dma_mask = &orion5x_xor_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(64),
|
|
.platform_data = (void *)&orion5x_xor1_data,
|
|
},
|
|
};
|
|
|
|
void __init orion5x_xor_init(void)
|
|
{
|
|
platform_device_register(&orion5x_xor_shared);
|
|
|
|
/*
|
|
* two engines can't do memset simultaneously, this limitation
|
|
* satisfied by removing memset support from one of the engines.
|
|
*/
|
|
dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
|
|
dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
|
|
platform_device_register(&orion5x_xor0_channel);
|
|
|
|
dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
|
|
dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
|
|
dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
|
|
platform_device_register(&orion5x_xor1_channel);
|
|
}
|
|
|
|
static struct resource orion5x_crypto_res[] = {
|
|
{
|
|
.name = "regs",
|
|
.start = ORION5X_CRYPTO_PHYS_BASE,
|
|
.end = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.name = "sram",
|
|
.start = ORION5X_SRAM_PHYS_BASE,
|
|
.end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.name = "crypto interrupt",
|
|
.start = IRQ_ORION5X_CESA,
|
|
.end = IRQ_ORION5X_CESA,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device orion5x_crypto_device = {
|
|
.name = "mv_crypto",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(orion5x_crypto_res),
|
|
.resource = orion5x_crypto_res,
|
|
};
|
|
|
|
static int __init orion5x_crypto_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = orion5x_setup_sram_win();
|
|
if (ret)
|
|
return ret;
|
|
|
|
return platform_device_register(&orion5x_crypto_device);
|
|
}
|
|
|
|
/*****************************************************************************
|
|
* Watchdog
|
|
****************************************************************************/
|
|
static struct orion_wdt_platform_data orion5x_wdt_data = {
|
|
.tclk = 0,
|
|
};
|
|
|
|
static struct platform_device orion5x_wdt_device = {
|
|
.name = "orion_wdt",
|
|
.id = -1,
|
|
.dev = {
|
|
.platform_data = &orion5x_wdt_data,
|
|
},
|
|
.num_resources = 0,
|
|
};
|
|
|
|
void __init orion5x_wdt_init(void)
|
|
{
|
|
orion5x_wdt_data.tclk = orion5x_tclk;
|
|
platform_device_register(&orion5x_wdt_device);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* Time handling
|
|
****************************************************************************/
|
|
int orion5x_tclk;
|
|
|
|
int __init orion5x_find_tclk(void)
|
|
{
|
|
u32 dev, rev;
|
|
|
|
orion5x_pcie_id(&dev, &rev);
|
|
if (dev == MV88F6183_DEV_ID &&
|
|
(readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
|
|
return 133333333;
|
|
|
|
return 166666667;
|
|
}
|
|
|
|
static void orion5x_timer_init(void)
|
|
{
|
|
orion5x_tclk = orion5x_find_tclk();
|
|
orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
|
|
}
|
|
|
|
struct sys_timer orion5x_timer = {
|
|
.init = orion5x_timer_init,
|
|
};
|
|
|
|
|
|
/*****************************************************************************
|
|
* General
|
|
****************************************************************************/
|
|
/*
|
|
* Identify device ID and rev from PCIe configuration header space '0'.
|
|
*/
|
|
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
|
|
{
|
|
orion5x_pcie_id(dev, rev);
|
|
|
|
if (*dev == MV88F5281_DEV_ID) {
|
|
if (*rev == MV88F5281_REV_D2) {
|
|
*dev_name = "MV88F5281-D2";
|
|
} else if (*rev == MV88F5281_REV_D1) {
|
|
*dev_name = "MV88F5281-D1";
|
|
} else if (*rev == MV88F5281_REV_D0) {
|
|
*dev_name = "MV88F5281-D0";
|
|
} else {
|
|
*dev_name = "MV88F5281-Rev-Unsupported";
|
|
}
|
|
} else if (*dev == MV88F5182_DEV_ID) {
|
|
if (*rev == MV88F5182_REV_A2) {
|
|
*dev_name = "MV88F5182-A2";
|
|
} else {
|
|
*dev_name = "MV88F5182-Rev-Unsupported";
|
|
}
|
|
} else if (*dev == MV88F5181_DEV_ID) {
|
|
if (*rev == MV88F5181_REV_B1) {
|
|
*dev_name = "MV88F5181-Rev-B1";
|
|
} else if (*rev == MV88F5181L_REV_A1) {
|
|
*dev_name = "MV88F5181L-Rev-A1";
|
|
} else {
|
|
*dev_name = "MV88F5181(L)-Rev-Unsupported";
|
|
}
|
|
} else if (*dev == MV88F6183_DEV_ID) {
|
|
if (*rev == MV88F6183_REV_B0) {
|
|
*dev_name = "MV88F6183-Rev-B0";
|
|
} else {
|
|
*dev_name = "MV88F6183-Rev-Unsupported";
|
|
}
|
|
} else {
|
|
*dev_name = "Device-Unknown";
|
|
}
|
|
}
|
|
|
|
void __init orion5x_init(void)
|
|
{
|
|
char *dev_name;
|
|
u32 dev, rev;
|
|
|
|
orion5x_id(&dev, &rev, &dev_name);
|
|
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
|
|
|
|
orion5x_eth_shared_data.t_clk = orion5x_tclk;
|
|
orion5x_spi_plat_data.tclk = orion5x_tclk;
|
|
orion5x_uart0_data[0].uartclk = orion5x_tclk;
|
|
orion5x_uart1_data[0].uartclk = orion5x_tclk;
|
|
|
|
/*
|
|
* Setup Orion address map
|
|
*/
|
|
orion5x_setup_cpu_mbus_bridge();
|
|
|
|
/*
|
|
* Don't issue "Wait for Interrupt" instruction if we are
|
|
* running on D0 5281 silicon.
|
|
*/
|
|
if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
|
|
printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
|
|
disable_hlt();
|
|
}
|
|
|
|
/*
|
|
* The 5082/5181l/5182/6082/6082l/6183 have crypto
|
|
* while 5180n/5181/5281 don't have crypto.
|
|
*/
|
|
if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
|
|
dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
|
|
orion5x_crypto_init();
|
|
|
|
/*
|
|
* Register watchdog driver
|
|
*/
|
|
orion5x_wdt_init();
|
|
}
|
|
|
|
/*
|
|
* Many orion-based systems have buggy bootloader implementations.
|
|
* This is a common fixup for bogus memory tags.
|
|
*/
|
|
void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
|
|
char **from, struct meminfo *meminfo)
|
|
{
|
|
for (; t->hdr.size; t = tag_next(t))
|
|
if (t->hdr.tag == ATAG_MEM &&
|
|
(!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
|
|
t->u.mem.start & ~PAGE_MASK)) {
|
|
printk(KERN_WARNING
|
|
"Clearing invalid memory bank %dKB@0x%08x\n",
|
|
t->u.mem.size / 1024, t->u.mem.start);
|
|
t->hdr.tag = 0;
|
|
}
|
|
}
|
|
|