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984 lines
28 KiB
984 lines
28 KiB
/*
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* linux/drivers/ide/pci/sis5513.c Version 0.16ac+vp Jun 18, 2003
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*
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* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
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* Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
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* May be copied or modified under the terms of the GNU General Public License
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*
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*
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* Thanks :
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*
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* SiS Taiwan : for direct support and hardware.
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* Daniela Engert : for initial ATA100 advices and numerous others.
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* John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
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* for checking code correctness, providing patches.
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*
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*
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* Original tests and design on the SiS620 chipset.
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* ATA100 tests and design on the SiS735 chipset.
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* ATA16/33 support from specs
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* ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
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* ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
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*
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* Documentation:
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* SiS chipset documentation available under NDA to companies only
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* (not to individuals).
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*/
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/*
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* The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
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* SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
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* or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
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*
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* Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
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* starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
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* can figure out that we have a more modern and more capable 5513 by looking
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* for the respective NorthBridge IDs.
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*
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* Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
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* into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
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* ID, while the now ATA-133 capable 5513 still has the same PCI ID.
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* Fortunately the 5513 can be 'unmasked' by fiddling with some config space
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* bits, changing its device id to the true one - 5517 for 961 and 5518 for
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* 962/963.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/irq.h>
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#include "ide-timing.h"
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#define DISPLAY_SIS_TIMINGS
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/* registers layout and init values are chipset family dependant */
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#define ATA_16 0x01
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#define ATA_33 0x02
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#define ATA_66 0x03
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#define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
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#define ATA_100 0x05
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#define ATA_133a 0x06 // SiS961b with 133 support
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#define ATA_133 0x07 // SiS962/963
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static u8 chipset_family;
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/*
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* Devices supported
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*/
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static const struct {
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const char *name;
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u16 host_id;
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u8 chipset_family;
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u8 flags;
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} SiSHostChipInfo[] = {
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{ "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
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{ "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
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{ "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
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{ "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
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{ "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
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{ "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
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{ "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
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{ "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
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{ "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
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{ "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
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{ "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
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{ "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
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{ "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
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{ "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
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{ "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
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{ "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
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{ "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
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{ "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
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{ "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
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{ "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
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{ "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
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};
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/* Cycle time bits and values vary across chip dma capabilities
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These three arrays hold the register layout and the values to set.
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Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
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/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
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static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
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static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
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static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
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{0,0,0,0,0,0,0}, /* no udma */
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{0,0,0,0,0,0,0}, /* no udma */
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{3,2,1,0,0,0,0}, /* ATA_33 */
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{7,5,3,2,1,0,0}, /* ATA_66 */
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{7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
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{11,7,5,4,2,1,0}, /* ATA_100 */
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{15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
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{15,10,7,5,3,2,1}, /* ATA_133 */
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};
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/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
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See SiS962 data sheet for more detail */
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static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
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{0,0,0,0,0,0,0}, /* no udma */
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{0,0,0,0,0,0,0}, /* no udma */
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{2,1,1,0,0,0,0},
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{4,3,2,1,0,0,0},
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{4,3,2,1,0,0,0},
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{6,4,3,1,1,1,0},
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{9,6,4,2,2,2,2},
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{9,6,4,2,2,2,2},
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};
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/* Initialize time, Active time, Recovery time vary across
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IDE clock settings. These 3 arrays hold the register value
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for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
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static u8 ini_time_value[][8] = {
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{0,0,0,0,0,0,0,0},
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{0,0,0,0,0,0,0,0},
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{2,1,0,0,0,1,0,0},
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{4,3,1,1,1,3,1,1},
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{4,3,1,1,1,3,1,1},
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{6,4,2,2,2,4,2,2},
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{9,6,3,3,3,6,3,3},
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{9,6,3,3,3,6,3,3},
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};
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static u8 act_time_value[][8] = {
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{0,0,0,0,0,0,0,0},
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{0,0,0,0,0,0,0,0},
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{9,9,9,2,2,7,2,2},
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{19,19,19,5,4,14,5,4},
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{19,19,19,5,4,14,5,4},
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{28,28,28,7,6,21,7,6},
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{38,38,38,10,9,28,10,9},
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{38,38,38,10,9,28,10,9},
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};
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static u8 rco_time_value[][8] = {
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{0,0,0,0,0,0,0,0},
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{0,0,0,0,0,0,0,0},
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{9,2,0,2,0,7,1,1},
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{19,5,1,5,2,16,3,2},
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{19,5,1,5,2,16,3,2},
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{30,9,3,9,4,25,6,4},
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{40,12,4,12,5,34,12,5},
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{40,12,4,12,5,34,12,5},
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};
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/*
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* Printing configuration
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*/
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/* Used for chipset type printing at boot time */
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static char* chipset_capability[] = {
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"ATA", "ATA 16",
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"ATA 33", "ATA 66",
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"ATA 100 (1st gen)", "ATA 100 (2nd gen)",
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"ATA 133 (1st gen)", "ATA 133 (2nd gen)"
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};
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#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
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#include <linux/stat.h>
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#include <linux/proc_fs.h>
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static u8 sis_proc = 0;
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static struct pci_dev *bmide_dev;
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static char* cable_type[] = {
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"80 pins",
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"40 pins"
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};
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static char* recovery_time[] ={
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"12 PCICLK", "1 PCICLK",
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"2 PCICLK", "3 PCICLK",
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"4 PCICLK", "5 PCICLCK",
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"6 PCICLK", "7 PCICLCK",
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"8 PCICLK", "9 PCICLCK",
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"10 PCICLK", "11 PCICLK",
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"13 PCICLK", "14 PCICLK",
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"15 PCICLK", "15 PCICLK"
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};
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static char* active_time[] = {
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"8 PCICLK", "1 PCICLCK",
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"2 PCICLK", "3 PCICLK",
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"4 PCICLK", "5 PCICLK",
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"6 PCICLK", "12 PCICLK"
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};
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static char* cycle_time[] = {
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"Reserved", "2 CLK",
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"3 CLK", "4 CLK",
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"5 CLK", "6 CLK",
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"7 CLK", "8 CLK",
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"9 CLK", "10 CLK",
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"11 CLK", "12 CLK",
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"13 CLK", "14 CLK",
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"15 CLK", "16 CLK"
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};
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/* Generic add master or slave info function */
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static char* get_drives_info (char *buffer, u8 pos)
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{
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u8 reg00, reg01, reg10, reg11; /* timing registers */
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u32 regdw0, regdw1;
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char* p = buffer;
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/* Postwrite/Prefetch */
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if (chipset_family < ATA_133) {
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pci_read_config_byte(bmide_dev, 0x4b, ®00);
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p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n",
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pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
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(reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
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p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
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(reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
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(reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
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pci_read_config_byte(bmide_dev, 0x40+2*pos, ®00);
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pci_read_config_byte(bmide_dev, 0x41+2*pos, ®01);
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pci_read_config_byte(bmide_dev, 0x44+2*pos, ®10);
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pci_read_config_byte(bmide_dev, 0x45+2*pos, ®11);
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} else {
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u32 reg54h;
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u8 drive_pci = 0x40;
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pci_read_config_dword(bmide_dev, 0x54, ®54h);
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if (reg54h & 0x40000000) {
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// Configuration space remapped to 0x70
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drive_pci = 0x70;
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}
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pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, ®dw0);
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pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, ®dw1);
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p += sprintf(p, "Drive %d:\n", pos);
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}
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/* UDMA */
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if (chipset_family >= ATA_133) {
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p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
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(regdw0 & 0x04) ? "Enabled" : "Disabled",
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(regdw1 & 0x04) ? "Enabled" : "Disabled");
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p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
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cycle_time[(regdw0 & 0xF0) >> 4],
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cycle_time[(regdw1 & 0xF0) >> 4]);
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} else if (chipset_family >= ATA_33) {
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p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
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(reg01 & 0x80) ? "Enabled" : "Disabled",
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(reg11 & 0x80) ? "Enabled" : "Disabled");
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p += sprintf(p, " UDMA Cycle Time ");
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switch(chipset_family) {
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case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
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case ATA_66:
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case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
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case ATA_100:
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case ATA_133a: p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
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default: p += sprintf(p, "?"); break;
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}
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p += sprintf(p, " \t UDMA Cycle Time ");
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switch(chipset_family) {
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case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
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case ATA_66:
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case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
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case ATA_100:
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case ATA_133a: p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
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default: p += sprintf(p, "?"); break;
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}
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p += sprintf(p, "\n");
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}
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if (chipset_family < ATA_133) { /* else case TODO */
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/* Data Active */
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p += sprintf(p, " Data Active Time ");
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switch(chipset_family) {
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case ATA_16: /* confirmed */
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case ATA_33:
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case ATA_66:
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case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
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case ATA_100:
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case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
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default: p += sprintf(p, "?"); break;
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}
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p += sprintf(p, " \t Data Active Time ");
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switch(chipset_family) {
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case ATA_16:
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case ATA_33:
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case ATA_66:
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case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
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case ATA_100:
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case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
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default: p += sprintf(p, "?"); break;
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}
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p += sprintf(p, "\n");
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/* Data Recovery */
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/* warning: may need (reg&0x07) for pre ATA66 chips */
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p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
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recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
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}
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return p;
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}
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static char* get_masters_info(char* buffer)
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{
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return get_drives_info(buffer, 0);
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}
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static char* get_slaves_info(char* buffer)
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{
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return get_drives_info(buffer, 1);
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}
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/* Main get_info, called on /proc/ide/sis reads */
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static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
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{
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char *p = buffer;
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int len;
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u8 reg;
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u16 reg2, reg3;
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p += sprintf(p, "\nSiS 5513 ");
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switch(chipset_family) {
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case ATA_16: p += sprintf(p, "DMA 16"); break;
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case ATA_33: p += sprintf(p, "Ultra 33"); break;
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case ATA_66: p += sprintf(p, "Ultra 66"); break;
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case ATA_100a:
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case ATA_100: p += sprintf(p, "Ultra 100"); break;
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case ATA_133a:
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case ATA_133: p += sprintf(p, "Ultra 133"); break;
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default: p+= sprintf(p, "Unknown???"); break;
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}
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p += sprintf(p, " chipset\n");
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p += sprintf(p, "--------------- Primary Channel "
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"---------------- Secondary Channel "
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"-------------\n");
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/* Status */
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pci_read_config_byte(bmide_dev, 0x4a, ®);
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if (chipset_family == ATA_133) {
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pci_read_config_word(bmide_dev, 0x50, ®2);
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pci_read_config_word(bmide_dev, 0x52, ®3);
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}
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p += sprintf(p, "Channel Status: ");
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if (chipset_family < ATA_66) {
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p += sprintf(p, "%s \t \t \t \t %s\n",
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(reg & 0x04) ? "On" : "Off",
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(reg & 0x02) ? "On" : "Off");
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} else if (chipset_family < ATA_133) {
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p += sprintf(p, "%s \t \t \t \t %s \n",
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(reg & 0x02) ? "On" : "Off",
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(reg & 0x04) ? "On" : "Off");
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} else { /* ATA_133 */
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p += sprintf(p, "%s \t \t \t \t %s \n",
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(reg2 & 0x02) ? "On" : "Off",
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(reg3 & 0x02) ? "On" : "Off");
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}
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|
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/* Operation Mode */
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pci_read_config_byte(bmide_dev, 0x09, ®);
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p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
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(reg & 0x01) ? "Native" : "Compatible",
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(reg & 0x04) ? "Native" : "Compatible");
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|
|
/* 80-pin cable ? */
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if (chipset_family >= ATA_133) {
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p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
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(reg2 & 0x01) ? cable_type[1] : cable_type[0],
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(reg3 & 0x01) ? cable_type[1] : cable_type[0]);
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} else if (chipset_family > ATA_33) {
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pci_read_config_byte(bmide_dev, 0x48, ®);
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p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
|
|
(reg & 0x10) ? cable_type[1] : cable_type[0],
|
|
(reg & 0x20) ? cable_type[1] : cable_type[0]);
|
|
}
|
|
|
|
/* Prefetch Count */
|
|
if (chipset_family < ATA_133) {
|
|
pci_read_config_word(bmide_dev, 0x4c, ®2);
|
|
pci_read_config_word(bmide_dev, 0x4e, ®3);
|
|
p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
|
|
reg2, reg3);
|
|
}
|
|
|
|
p = get_masters_info(p);
|
|
p = get_slaves_info(p);
|
|
|
|
len = (p - buffer) - offset;
|
|
*addr = buffer + offset;
|
|
|
|
return len > count ? count : len;
|
|
}
|
|
#endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
|
|
|
|
static u8 sis5513_ratemask (ide_drive_t *drive)
|
|
{
|
|
u8 rates[] = { 0, 0, 1, 2, 3, 3, 4, 4 };
|
|
u8 mode = rates[chipset_family];
|
|
|
|
if (!eighty_ninty_three(drive))
|
|
mode = min(mode, (u8)1);
|
|
return mode;
|
|
}
|
|
|
|
/*
|
|
* Configuration functions
|
|
*/
|
|
/* Enables per-drive prefetch and postwrite */
|
|
static void config_drive_art_rwp (ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
struct pci_dev *dev = hwif->pci_dev;
|
|
|
|
u8 reg4bh = 0;
|
|
u8 rw_prefetch = (0x11 << drive->dn);
|
|
|
|
if (drive->media != ide_disk)
|
|
return;
|
|
pci_read_config_byte(dev, 0x4b, ®4bh);
|
|
|
|
if ((reg4bh & rw_prefetch) != rw_prefetch)
|
|
pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
|
|
}
|
|
|
|
|
|
/* Set per-drive active and recovery time */
|
|
static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
|
|
{
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
struct pci_dev *dev = hwif->pci_dev;
|
|
|
|
u8 timing, drive_pci, test1, test2;
|
|
|
|
u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
|
|
u16 xfer_pio = drive->id->eide_pio_modes;
|
|
|
|
config_drive_art_rwp(drive);
|
|
pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
|
|
|
|
if (xfer_pio> 4)
|
|
xfer_pio = 0;
|
|
|
|
if (drive->id->eide_pio_iordy > 0) {
|
|
for (xfer_pio = 5;
|
|
(xfer_pio > 0) &&
|
|
(drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
|
|
xfer_pio--);
|
|
} else {
|
|
xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
|
|
(drive->id->eide_pio_modes & 2) ? 0x04 :
|
|
(drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
|
|
}
|
|
|
|
timing = (xfer_pio >= pio) ? xfer_pio : pio;
|
|
|
|
/* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
|
|
drive_pci = 0x40;
|
|
/* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
|
|
if (chipset_family >= ATA_133) {
|
|
u32 reg54h;
|
|
pci_read_config_dword(dev, 0x54, ®54h);
|
|
if (reg54h & 0x40000000) drive_pci = 0x70;
|
|
drive_pci += ((drive->dn)*0x4);
|
|
} else {
|
|
drive_pci += ((drive->dn)*0x2);
|
|
}
|
|
|
|
/* register layout changed with newer ATA100 chips */
|
|
if (chipset_family < ATA_100) {
|
|
pci_read_config_byte(dev, drive_pci, &test1);
|
|
pci_read_config_byte(dev, drive_pci+1, &test2);
|
|
|
|
/* Clear active and recovery timings */
|
|
test1 &= ~0x0F;
|
|
test2 &= ~0x07;
|
|
|
|
switch(timing) {
|
|
case 4: test1 |= 0x01; test2 |= 0x03; break;
|
|
case 3: test1 |= 0x03; test2 |= 0x03; break;
|
|
case 2: test1 |= 0x04; test2 |= 0x04; break;
|
|
case 1: test1 |= 0x07; test2 |= 0x06; break;
|
|
default: break;
|
|
}
|
|
pci_write_config_byte(dev, drive_pci, test1);
|
|
pci_write_config_byte(dev, drive_pci+1, test2);
|
|
} else if (chipset_family < ATA_133) {
|
|
switch(timing) { /* active recovery
|
|
v v */
|
|
case 4: test1 = 0x30|0x01; break;
|
|
case 3: test1 = 0x30|0x03; break;
|
|
case 2: test1 = 0x40|0x04; break;
|
|
case 1: test1 = 0x60|0x07; break;
|
|
default: break;
|
|
}
|
|
pci_write_config_byte(dev, drive_pci, test1);
|
|
} else { /* ATA_133 */
|
|
u32 test3;
|
|
pci_read_config_dword(dev, drive_pci, &test3);
|
|
test3 &= 0xc0c00fff;
|
|
if (test3 & 0x08) {
|
|
test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12;
|
|
test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16;
|
|
test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24;
|
|
} else {
|
|
test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12;
|
|
test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16;
|
|
test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24;
|
|
}
|
|
pci_write_config_dword(dev, drive_pci, test3);
|
|
}
|
|
}
|
|
|
|
static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
|
|
{
|
|
if (pio == 255)
|
|
pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
|
|
config_art_rwp_pio(drive, pio);
|
|
return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4));
|
|
}
|
|
|
|
static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
|
|
{
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
struct pci_dev *dev = hwif->pci_dev;
|
|
|
|
u8 drive_pci, reg, speed;
|
|
u32 regdw;
|
|
|
|
speed = ide_rate_filter(sis5513_ratemask(drive), xferspeed);
|
|
|
|
/* See config_art_rwp_pio for drive pci config registers */
|
|
drive_pci = 0x40;
|
|
if (chipset_family >= ATA_133) {
|
|
u32 reg54h;
|
|
pci_read_config_dword(dev, 0x54, ®54h);
|
|
if (reg54h & 0x40000000) drive_pci = 0x70;
|
|
drive_pci += ((drive->dn)*0x4);
|
|
pci_read_config_dword(dev, (unsigned long)drive_pci, ®dw);
|
|
/* Disable UDMA bit for non UDMA modes on UDMA chips */
|
|
if (speed < XFER_UDMA_0) {
|
|
regdw &= 0xfffffffb;
|
|
pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
|
|
}
|
|
|
|
} else {
|
|
drive_pci += ((drive->dn)*0x2);
|
|
pci_read_config_byte(dev, drive_pci+1, ®);
|
|
/* Disable UDMA bit for non UDMA modes on UDMA chips */
|
|
if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
|
|
reg &= 0x7F;
|
|
pci_write_config_byte(dev, drive_pci+1, reg);
|
|
}
|
|
}
|
|
|
|
/* Config chip for mode */
|
|
switch(speed) {
|
|
case XFER_UDMA_6:
|
|
case XFER_UDMA_5:
|
|
case XFER_UDMA_4:
|
|
case XFER_UDMA_3:
|
|
case XFER_UDMA_2:
|
|
case XFER_UDMA_1:
|
|
case XFER_UDMA_0:
|
|
if (chipset_family >= ATA_133) {
|
|
regdw |= 0x04;
|
|
regdw &= 0xfffff00f;
|
|
/* check if ATA133 enable */
|
|
if (regdw & 0x08) {
|
|
regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
|
|
regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
|
|
} else {
|
|
/* if ATA133 disable, we should not set speed above UDMA5 */
|
|
if (speed > XFER_UDMA_5)
|
|
speed = XFER_UDMA_5;
|
|
regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
|
|
regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
|
|
}
|
|
pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
|
|
} else {
|
|
/* Force the UDMA bit on if we want to use UDMA */
|
|
reg |= 0x80;
|
|
/* clean reg cycle time bits */
|
|
reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
|
|
<< cycle_time_offset[chipset_family]);
|
|
/* set reg cycle time bits */
|
|
reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
|
|
<< cycle_time_offset[chipset_family];
|
|
pci_write_config_byte(dev, drive_pci+1, reg);
|
|
}
|
|
break;
|
|
case XFER_MW_DMA_2:
|
|
case XFER_MW_DMA_1:
|
|
case XFER_MW_DMA_0:
|
|
case XFER_SW_DMA_2:
|
|
case XFER_SW_DMA_1:
|
|
case XFER_SW_DMA_0:
|
|
break;
|
|
case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
|
|
case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
|
|
case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
|
|
case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
|
|
case XFER_PIO_0:
|
|
default: return((int) config_chipset_for_pio(drive, 0));
|
|
}
|
|
|
|
return ((int) ide_config_drive_speed(drive, speed));
|
|
}
|
|
|
|
static void sis5513_tune_drive (ide_drive_t *drive, u8 pio)
|
|
{
|
|
(void) config_chipset_for_pio(drive, pio);
|
|
}
|
|
|
|
/*
|
|
* ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
|
|
*/
|
|
static int config_chipset_for_dma (ide_drive_t *drive)
|
|
{
|
|
u8 speed = ide_dma_speed(drive, sis5513_ratemask(drive));
|
|
|
|
#ifdef DEBUG
|
|
printk("SIS5513: config_chipset_for_dma, drive %d, ultra %x\n",
|
|
drive->dn, drive->id->dma_ultra);
|
|
#endif
|
|
|
|
if (!(speed))
|
|
return 0;
|
|
|
|
sis5513_tune_chipset(drive, speed);
|
|
return ide_dma_enable(drive);
|
|
}
|
|
|
|
static int sis5513_config_drive_xfer_rate (ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
struct hd_driveid *id = drive->id;
|
|
|
|
drive->init_speed = 0;
|
|
|
|
if (id && (id->capability & 1) && drive->autodma) {
|
|
|
|
if (ide_use_dma(drive)) {
|
|
if (config_chipset_for_dma(drive))
|
|
return hwif->ide_dma_on(drive);
|
|
}
|
|
|
|
goto fast_ata_pio;
|
|
|
|
} else if ((id->capability & 8) || (id->field_valid & 2)) {
|
|
fast_ata_pio:
|
|
sis5513_tune_drive(drive, 5);
|
|
return hwif->ide_dma_off_quietly(drive);
|
|
}
|
|
/* IORDY not supported */
|
|
return 0;
|
|
}
|
|
|
|
/* initiates/aborts (U)DMA read/write operations on a drive. */
|
|
static int sis5513_config_xfer_rate (ide_drive_t *drive)
|
|
{
|
|
config_drive_art_rwp(drive);
|
|
config_art_rwp_pio(drive, 5);
|
|
return sis5513_config_drive_xfer_rate(drive);
|
|
}
|
|
|
|
/*
|
|
Future simpler config_xfer_rate :
|
|
When ide_find_best_mode is made bad-drive aware
|
|
- remove config_drive_xfer_rate and config_chipset_for_dma,
|
|
- replace config_xfer_rate with the following
|
|
|
|
static int sis5513_config_xfer_rate (ide_drive_t *drive)
|
|
{
|
|
u16 w80 = HWIF(drive)->udma_four;
|
|
u16 speed;
|
|
|
|
config_drive_art_rwp(drive);
|
|
config_art_rwp_pio(drive, 5);
|
|
|
|
speed = ide_find_best_mode(drive,
|
|
XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
|
|
(chipset_family >= ATA_33 ? XFER_UDMA : 0) |
|
|
(w80 && chipset_family >= ATA_66 ? XFER_UDMA_66 : 0) |
|
|
(w80 && chipset_family >= ATA_100a ? XFER_UDMA_100 : 0) |
|
|
(w80 && chipset_family >= ATA_133a ? XFER_UDMA_133 : 0));
|
|
|
|
sis5513_tune_chipset(drive, speed);
|
|
|
|
if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
|
|
return HWIF(drive)->ide_dma_on(drive);
|
|
return HWIF(drive)->ide_dma_off_quietly(drive);
|
|
}
|
|
*/
|
|
|
|
/* Chip detection and general config */
|
|
static unsigned int __init init_chipset_sis5513 (struct pci_dev *dev, const char *name)
|
|
{
|
|
struct pci_dev *host;
|
|
int i = 0;
|
|
|
|
chipset_family = 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
|
|
|
|
host = pci_find_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
|
|
|
|
if (!host)
|
|
continue;
|
|
|
|
chipset_family = SiSHostChipInfo[i].chipset_family;
|
|
|
|
/* Special case for SiS630 : 630S/ET is ATA_100a */
|
|
if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
|
|
u8 hostrev;
|
|
pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
|
|
if (hostrev >= 0x30)
|
|
chipset_family = ATA_100a;
|
|
}
|
|
|
|
printk(KERN_INFO "SIS5513: %s %s controller\n",
|
|
SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
|
|
}
|
|
|
|
if (!chipset_family) { /* Belongs to pci-quirks */
|
|
|
|
u32 idemisc;
|
|
u16 trueid;
|
|
|
|
/* Disable ID masking and register remapping */
|
|
pci_read_config_dword(dev, 0x54, &idemisc);
|
|
pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
|
|
pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
|
|
pci_write_config_dword(dev, 0x54, idemisc);
|
|
|
|
if (trueid == 0x5518) {
|
|
printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
|
|
chipset_family = ATA_133;
|
|
|
|
/* Check for 5513 compability mapping
|
|
* We must use this, else the port enabled code will fail,
|
|
* as it expects the enablebits at 0x4a.
|
|
*/
|
|
if ((idemisc & 0x40000000) == 0) {
|
|
pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
|
|
printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!chipset_family) { /* Belongs to pci-quirks */
|
|
|
|
struct pci_dev *lpc_bridge;
|
|
u16 trueid;
|
|
u8 prefctl;
|
|
u8 idecfg;
|
|
u8 sbrev;
|
|
|
|
pci_read_config_byte(dev, 0x4a, &idecfg);
|
|
pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
|
|
pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
|
|
pci_write_config_byte(dev, 0x4a, idecfg);
|
|
|
|
if (trueid == 0x5517) { /* SiS 961/961B */
|
|
|
|
lpc_bridge = pci_find_slot(0x00, 0x10); /* Bus 0, Dev 2, Fn 0 */
|
|
pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
|
|
pci_read_config_byte(dev, 0x49, &prefctl);
|
|
|
|
if (sbrev == 0x10 && (prefctl & 0x80)) {
|
|
printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
|
|
chipset_family = ATA_133a;
|
|
} else {
|
|
printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
|
|
chipset_family = ATA_100;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!chipset_family)
|
|
return -1;
|
|
|
|
/* Make general config ops here
|
|
1/ tell IDE channels to operate in Compatibility mode only
|
|
2/ tell old chips to allow per drive IDE timings */
|
|
|
|
{
|
|
u8 reg;
|
|
u16 regw;
|
|
|
|
switch(chipset_family) {
|
|
case ATA_133:
|
|
/* SiS962 operation mode */
|
|
pci_read_config_word(dev, 0x50, ®w);
|
|
if (regw & 0x08)
|
|
pci_write_config_word(dev, 0x50, regw&0xfff7);
|
|
pci_read_config_word(dev, 0x52, ®w);
|
|
if (regw & 0x08)
|
|
pci_write_config_word(dev, 0x52, regw&0xfff7);
|
|
break;
|
|
case ATA_133a:
|
|
case ATA_100:
|
|
/* Fixup latency */
|
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
|
|
/* Set compatibility bit */
|
|
pci_read_config_byte(dev, 0x49, ®);
|
|
if (!(reg & 0x01)) {
|
|
pci_write_config_byte(dev, 0x49, reg|0x01);
|
|
}
|
|
break;
|
|
case ATA_100a:
|
|
case ATA_66:
|
|
/* Fixup latency */
|
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
|
|
|
|
/* On ATA_66 chips the bit was elsewhere */
|
|
pci_read_config_byte(dev, 0x52, ®);
|
|
if (!(reg & 0x04)) {
|
|
pci_write_config_byte(dev, 0x52, reg|0x04);
|
|
}
|
|
break;
|
|
case ATA_33:
|
|
/* On ATA_33 we didn't have a single bit to set */
|
|
pci_read_config_byte(dev, 0x09, ®);
|
|
if ((reg & 0x0f) != 0x00) {
|
|
pci_write_config_byte(dev, 0x09, reg&0xf0);
|
|
}
|
|
case ATA_16:
|
|
/* force per drive recovery and active timings
|
|
needed on ATA_33 and below chips */
|
|
pci_read_config_byte(dev, 0x52, ®);
|
|
if (!(reg & 0x08)) {
|
|
pci_write_config_byte(dev, 0x52, reg|0x08);
|
|
}
|
|
break;
|
|
}
|
|
|
|
#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
|
|
if (!sis_proc) {
|
|
sis_proc = 1;
|
|
bmide_dev = dev;
|
|
ide_pci_create_host_proc("sis", sis_get_info);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int __init ata66_sis5513 (ide_hwif_t *hwif)
|
|
{
|
|
u8 ata66 = 0;
|
|
|
|
if (chipset_family >= ATA_133) {
|
|
u16 regw = 0;
|
|
u16 reg_addr = hwif->channel ? 0x52: 0x50;
|
|
pci_read_config_word(hwif->pci_dev, reg_addr, ®w);
|
|
ata66 = (regw & 0x8000) ? 0 : 1;
|
|
} else if (chipset_family >= ATA_66) {
|
|
u8 reg48h = 0;
|
|
u8 mask = hwif->channel ? 0x20 : 0x10;
|
|
pci_read_config_byte(hwif->pci_dev, 0x48, ®48h);
|
|
ata66 = (reg48h & mask) ? 0 : 1;
|
|
}
|
|
return ata66;
|
|
}
|
|
|
|
static void __init init_hwif_sis5513 (ide_hwif_t *hwif)
|
|
{
|
|
hwif->autodma = 0;
|
|
|
|
if (!hwif->irq)
|
|
hwif->irq = hwif->channel ? 15 : 14;
|
|
|
|
hwif->tuneproc = &sis5513_tune_drive;
|
|
hwif->speedproc = &sis5513_tune_chipset;
|
|
|
|
if (!(hwif->dma_base)) {
|
|
hwif->drives[0].autotune = 1;
|
|
hwif->drives[1].autotune = 1;
|
|
return;
|
|
}
|
|
|
|
hwif->atapi_dma = 1;
|
|
hwif->ultra_mask = 0x7f;
|
|
hwif->mwdma_mask = 0x07;
|
|
hwif->swdma_mask = 0x07;
|
|
|
|
if (!chipset_family)
|
|
return;
|
|
|
|
if (!(hwif->udma_four))
|
|
hwif->udma_four = ata66_sis5513(hwif);
|
|
|
|
if (chipset_family > ATA_16) {
|
|
hwif->ide_dma_check = &sis5513_config_xfer_rate;
|
|
if (!noautodma)
|
|
hwif->autodma = 1;
|
|
}
|
|
hwif->drives[0].autodma = hwif->autodma;
|
|
hwif->drives[1].autodma = hwif->autodma;
|
|
return;
|
|
}
|
|
|
|
static ide_pci_device_t sis5513_chipset __devinitdata = {
|
|
.name = "SIS5513",
|
|
.init_chipset = init_chipset_sis5513,
|
|
.init_hwif = init_hwif_sis5513,
|
|
.channels = 2,
|
|
.autodma = NOAUTODMA,
|
|
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
|
|
.bootable = ON_BOARD,
|
|
};
|
|
|
|
static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
return ide_setup_pci_device(dev, &sis5513_chipset);
|
|
}
|
|
|
|
static struct pci_device_id sis5513_pci_tbl[] = {
|
|
{ PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
|
|
{ PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
|
|
{ 0, },
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
|
|
|
|
static struct pci_driver driver = {
|
|
.name = "SIS_IDE",
|
|
.id_table = sis5513_pci_tbl,
|
|
.probe = sis5513_init_one,
|
|
};
|
|
|
|
static int sis5513_ide_init(void)
|
|
{
|
|
return ide_pci_register_driver(&driver);
|
|
}
|
|
|
|
module_init(sis5513_ide_init);
|
|
|
|
MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
|
|
MODULE_DESCRIPTION("PCI driver module for SIS IDE");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
/*
|
|
* TODO:
|
|
* - CLEANUP
|
|
* - Use drivers/ide/ide-timing.h !
|
|
* - More checks in the config registers (force values instead of
|
|
* relying on the BIOS setting them correctly).
|
|
* - Further optimisations ?
|
|
* . for example ATA66+ regs 0x48 & 0x4A
|
|
*/
|
|
|