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18 lines
721 B
18 lines
721 B
Device Tree Clock bindings for Altera's SoCFPGA platform
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"altr,socfpga-pll-clock" - for a PLL clock
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"altr,socfpga-perip-clock" - The peripheral clock divided from the
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PLL clock.
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- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
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- clocks : shall be the input parent clock phandle for the clock. This is
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either an oscillator or a pll output.
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- #clock-cells : from common clock binding, shall be set to 0.
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Optional properties:
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- fixed-divider : If clocks have a fixed divider value, use this property.
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