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233 lines
7.8 KiB
233 lines
7.8 KiB
/*******************************************************************************
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STMMAC Common Header File
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include "descs.h"
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#include <linux/netdevice.h>
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struct stmmac_extra_stats {
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/* Transmit errors */
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unsigned long tx_underflow ____cacheline_aligned;
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unsigned long tx_carrier;
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unsigned long tx_losscarrier;
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unsigned long tx_heartbeat;
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unsigned long tx_deferred;
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unsigned long tx_vlan;
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unsigned long tx_jabber;
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unsigned long tx_frame_flushed;
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unsigned long tx_payload_error;
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unsigned long tx_ip_header_error;
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/* Receive errors */
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unsigned long rx_desc;
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unsigned long rx_partial;
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unsigned long rx_runt;
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unsigned long rx_toolong;
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unsigned long rx_collision;
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unsigned long rx_crc;
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unsigned long rx_length;
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unsigned long rx_mii;
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unsigned long rx_multicast;
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unsigned long rx_gmac_overflow;
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unsigned long rx_watchdog;
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unsigned long da_rx_filter_fail;
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unsigned long sa_rx_filter_fail;
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unsigned long rx_missed_cntr;
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unsigned long rx_overflow_cntr;
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unsigned long rx_vlan;
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/* Tx/Rx IRQ errors */
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unsigned long tx_undeflow_irq;
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unsigned long tx_process_stopped_irq;
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unsigned long tx_jabber_irq;
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unsigned long rx_overflow_irq;
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unsigned long rx_buf_unav_irq;
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unsigned long rx_process_stopped_irq;
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unsigned long rx_watchdog_irq;
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unsigned long tx_early_irq;
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unsigned long fatal_bus_error_irq;
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/* Extra info */
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unsigned long threshold;
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unsigned long tx_pkt_n;
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unsigned long rx_pkt_n;
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unsigned long poll_n;
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unsigned long sched_timer_n;
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unsigned long normal_irq_n;
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};
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#define HASH_TABLE_SIZE 64
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#define PAUSE_TIME 0x200
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/* Flow Control defines */
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#define FLOW_OFF 0
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#define FLOW_RX 1
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#define FLOW_TX 2
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#define FLOW_AUTO (FLOW_TX | FLOW_RX)
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#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
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#define HW_CSUM 1
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#define NO_HW_CSUM 0
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enum rx_frame_status { /* IPC status */
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good_frame = 0,
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discard_frame = 1,
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csum_none = 2,
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};
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enum tx_dma_irq_status {
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tx_hard_error = 1,
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tx_hard_error_bump_tc = 2,
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handle_tx_rx = 3,
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};
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/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
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#define BUF_SIZE_16KiB 16384
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#define BUF_SIZE_8KiB 8192
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#define BUF_SIZE_4KiB 4096
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#define BUF_SIZE_2KiB 2048
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/* Power Down and WOL */
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#define PMT_NOT_SUPPORTED 0
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#define PMT_SUPPORTED 1
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/* Common MAC defines */
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#define MAC_CTRL_REG 0x00000000 /* MAC Control */
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#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
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#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
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/* MAC Management Counters register */
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#define MMC_CONTROL 0x00000100 /* MMC Control */
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#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
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#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
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#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
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#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
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#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
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#define MMC_CONTROL_MAX_FRM_SHIFT 3
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#define MMC_CONTROL_MAX_FRAME 0x7FF
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struct stmmac_desc_ops {
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/* DMA RX descriptor ring initialization */
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void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
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int disable_rx_ic);
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/* DMA TX descriptor ring initialization */
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void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
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/* Invoked by the xmit function to prepare the tx descriptor */
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void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
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int csum_flag);
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/* Set/get the owner of the descriptor */
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void (*set_tx_owner) (struct dma_desc *p);
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int (*get_tx_owner) (struct dma_desc *p);
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/* Invoked by the xmit function to close the tx descriptor */
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void (*close_tx_desc) (struct dma_desc *p);
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/* Clean the tx descriptor as soon as the tx irq is received */
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void (*release_tx_desc) (struct dma_desc *p);
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/* Clear interrupt on tx frame completion. When this bit is
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* set an interrupt happens as soon as the frame is transmitted */
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void (*clear_tx_ic) (struct dma_desc *p);
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/* Last tx segment reports the transmit status */
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int (*get_tx_ls) (struct dma_desc *p);
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/* Return the transmit status looking at the TDES1 */
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int (*tx_status) (void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p, unsigned long ioaddr);
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/* Get the buffer size from the descriptor */
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int (*get_tx_len) (struct dma_desc *p);
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/* Handle extra events on specific interrupts hw dependent */
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int (*get_rx_owner) (struct dma_desc *p);
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void (*set_rx_owner) (struct dma_desc *p);
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/* Get the receive frame size */
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int (*get_rx_frame_len) (struct dma_desc *p);
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/* Return the reception status looking at the RDES1 */
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int (*rx_status) (void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p);
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};
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struct stmmac_dma_ops {
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/* DMA core initialization */
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int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
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/* Dump DMA registers */
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void (*dump_regs) (unsigned long ioaddr);
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/* Set tx/rx threshold in the csr6 register
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* An invalid value enables the store-and-forward mode */
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void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
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/* To track extra statistic (if supported) */
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void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
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unsigned long ioaddr);
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void (*enable_dma_transmission) (unsigned long ioaddr);
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void (*enable_dma_irq) (unsigned long ioaddr);
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void (*disable_dma_irq) (unsigned long ioaddr);
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void (*start_tx) (unsigned long ioaddr);
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void (*stop_tx) (unsigned long ioaddr);
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void (*start_rx) (unsigned long ioaddr);
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void (*stop_rx) (unsigned long ioaddr);
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int (*dma_interrupt) (unsigned long ioaddr,
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struct stmmac_extra_stats *x);
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};
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struct stmmac_ops {
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/* MAC core initialization */
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void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
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/* Dump MAC registers */
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void (*dump_regs) (unsigned long ioaddr);
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/* Handle extra events on specific interrupts hw dependent */
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void (*host_irq_status) (unsigned long ioaddr);
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/* Multicast filter setting */
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void (*set_filter) (struct net_device *dev);
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/* Flow control setting */
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void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex,
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unsigned int fc, unsigned int pause_time);
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/* Set power management mode (e.g. magic frame) */
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void (*pmt) (unsigned long ioaddr, unsigned long mode);
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/* Set/Get Unicast MAC addresses */
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void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr,
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unsigned int reg_n);
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void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr,
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unsigned int reg_n);
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};
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struct mac_link {
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int port;
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int duplex;
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int speed;
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};
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struct mii_regs {
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unsigned int addr; /* MII Address */
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unsigned int data; /* MII Data */
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};
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struct mac_device_info {
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struct stmmac_ops *mac;
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struct stmmac_desc_ops *desc;
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struct stmmac_dma_ops *dma;
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unsigned int pmt; /* support Power-Down */
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struct mii_regs mii; /* MII register Addresses */
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struct mac_link link;
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};
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struct mac_device_info *dwmac1000_setup(unsigned long addr);
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struct mac_device_info *dwmac100_setup(unsigned long addr);
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extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
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unsigned int high, unsigned int low);
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extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
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unsigned int high, unsigned int low);
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