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436 lines
14 KiB
436 lines
14 KiB
#ifndef __dma_defs_h
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#define __dma_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
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* id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
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* last modfied: Mon Apr 11 16:06:51 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
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* id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope dma */
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/* Register rw_data, scope dma, type rw */
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typedef unsigned int reg_dma_rw_data;
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#define REG_RD_ADDR_dma_rw_data 0
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#define REG_WR_ADDR_dma_rw_data 0
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/* Register rw_data_next, scope dma, type rw */
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typedef unsigned int reg_dma_rw_data_next;
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#define REG_RD_ADDR_dma_rw_data_next 4
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#define REG_WR_ADDR_dma_rw_data_next 4
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/* Register rw_data_buf, scope dma, type rw */
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typedef unsigned int reg_dma_rw_data_buf;
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#define REG_RD_ADDR_dma_rw_data_buf 8
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#define REG_WR_ADDR_dma_rw_data_buf 8
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/* Register rw_data_ctrl, scope dma, type rw */
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typedef struct {
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unsigned int eol : 1;
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unsigned int dummy1 : 2;
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unsigned int out_eop : 1;
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unsigned int intr : 1;
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unsigned int wait : 1;
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unsigned int dummy2 : 26;
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} reg_dma_rw_data_ctrl;
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#define REG_RD_ADDR_dma_rw_data_ctrl 12
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#define REG_WR_ADDR_dma_rw_data_ctrl 12
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/* Register rw_data_stat, scope dma, type rw */
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typedef struct {
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unsigned int dummy1 : 3;
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unsigned int in_eop : 1;
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unsigned int dummy2 : 28;
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} reg_dma_rw_data_stat;
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#define REG_RD_ADDR_dma_rw_data_stat 16
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#define REG_WR_ADDR_dma_rw_data_stat 16
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/* Register rw_data_md, scope dma, type rw */
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typedef struct {
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unsigned int md : 16;
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unsigned int dummy1 : 16;
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} reg_dma_rw_data_md;
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#define REG_RD_ADDR_dma_rw_data_md 20
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#define REG_WR_ADDR_dma_rw_data_md 20
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/* Register rw_data_md_s, scope dma, type rw */
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typedef struct {
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unsigned int md_s : 16;
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unsigned int dummy1 : 16;
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} reg_dma_rw_data_md_s;
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#define REG_RD_ADDR_dma_rw_data_md_s 24
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#define REG_WR_ADDR_dma_rw_data_md_s 24
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/* Register rw_data_after, scope dma, type rw */
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typedef unsigned int reg_dma_rw_data_after;
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#define REG_RD_ADDR_dma_rw_data_after 28
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#define REG_WR_ADDR_dma_rw_data_after 28
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/* Register rw_ctxt, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt;
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#define REG_RD_ADDR_dma_rw_ctxt 32
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#define REG_WR_ADDR_dma_rw_ctxt 32
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/* Register rw_ctxt_next, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt_next;
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#define REG_RD_ADDR_dma_rw_ctxt_next 36
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#define REG_WR_ADDR_dma_rw_ctxt_next 36
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/* Register rw_ctxt_ctrl, scope dma, type rw */
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typedef struct {
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unsigned int eol : 1;
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unsigned int dummy1 : 3;
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unsigned int intr : 1;
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unsigned int dummy2 : 1;
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unsigned int store_mode : 1;
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unsigned int en : 1;
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unsigned int dummy3 : 24;
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} reg_dma_rw_ctxt_ctrl;
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#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
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#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
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/* Register rw_ctxt_stat, scope dma, type rw */
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typedef struct {
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unsigned int dummy1 : 7;
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unsigned int dis : 1;
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unsigned int dummy2 : 24;
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} reg_dma_rw_ctxt_stat;
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#define REG_RD_ADDR_dma_rw_ctxt_stat 44
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#define REG_WR_ADDR_dma_rw_ctxt_stat 44
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/* Register rw_ctxt_md0, scope dma, type rw */
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typedef struct {
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unsigned int md0 : 16;
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unsigned int dummy1 : 16;
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} reg_dma_rw_ctxt_md0;
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#define REG_RD_ADDR_dma_rw_ctxt_md0 48
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#define REG_WR_ADDR_dma_rw_ctxt_md0 48
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/* Register rw_ctxt_md0_s, scope dma, type rw */
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typedef struct {
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unsigned int md0_s : 16;
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unsigned int dummy1 : 16;
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} reg_dma_rw_ctxt_md0_s;
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#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
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#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
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/* Register rw_ctxt_md1, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt_md1;
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#define REG_RD_ADDR_dma_rw_ctxt_md1 56
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#define REG_WR_ADDR_dma_rw_ctxt_md1 56
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/* Register rw_ctxt_md1_s, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt_md1_s;
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#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
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#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
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/* Register rw_ctxt_md2, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt_md2;
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#define REG_RD_ADDR_dma_rw_ctxt_md2 64
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#define REG_WR_ADDR_dma_rw_ctxt_md2 64
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/* Register rw_ctxt_md2_s, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt_md2_s;
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#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
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#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
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/* Register rw_ctxt_md3, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt_md3;
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#define REG_RD_ADDR_dma_rw_ctxt_md3 72
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#define REG_WR_ADDR_dma_rw_ctxt_md3 72
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/* Register rw_ctxt_md3_s, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt_md3_s;
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#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
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#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
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/* Register rw_ctxt_md4, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt_md4;
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#define REG_RD_ADDR_dma_rw_ctxt_md4 80
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#define REG_WR_ADDR_dma_rw_ctxt_md4 80
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/* Register rw_ctxt_md4_s, scope dma, type rw */
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typedef unsigned int reg_dma_rw_ctxt_md4_s;
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#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
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#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
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/* Register rw_saved_data, scope dma, type rw */
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typedef unsigned int reg_dma_rw_saved_data;
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#define REG_RD_ADDR_dma_rw_saved_data 88
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#define REG_WR_ADDR_dma_rw_saved_data 88
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/* Register rw_saved_data_buf, scope dma, type rw */
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typedef unsigned int reg_dma_rw_saved_data_buf;
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#define REG_RD_ADDR_dma_rw_saved_data_buf 92
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#define REG_WR_ADDR_dma_rw_saved_data_buf 92
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/* Register rw_group, scope dma, type rw */
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typedef unsigned int reg_dma_rw_group;
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#define REG_RD_ADDR_dma_rw_group 96
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#define REG_WR_ADDR_dma_rw_group 96
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/* Register rw_group_next, scope dma, type rw */
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typedef unsigned int reg_dma_rw_group_next;
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#define REG_RD_ADDR_dma_rw_group_next 100
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#define REG_WR_ADDR_dma_rw_group_next 100
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/* Register rw_group_ctrl, scope dma, type rw */
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typedef struct {
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unsigned int eol : 1;
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unsigned int tol : 1;
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unsigned int bol : 1;
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unsigned int dummy1 : 1;
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unsigned int intr : 1;
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unsigned int dummy2 : 2;
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unsigned int en : 1;
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unsigned int dummy3 : 24;
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} reg_dma_rw_group_ctrl;
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#define REG_RD_ADDR_dma_rw_group_ctrl 104
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#define REG_WR_ADDR_dma_rw_group_ctrl 104
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/* Register rw_group_stat, scope dma, type rw */
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typedef struct {
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unsigned int dummy1 : 7;
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unsigned int dis : 1;
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unsigned int dummy2 : 24;
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} reg_dma_rw_group_stat;
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#define REG_RD_ADDR_dma_rw_group_stat 108
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#define REG_WR_ADDR_dma_rw_group_stat 108
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/* Register rw_group_md, scope dma, type rw */
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typedef struct {
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unsigned int md : 16;
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unsigned int dummy1 : 16;
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} reg_dma_rw_group_md;
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#define REG_RD_ADDR_dma_rw_group_md 112
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#define REG_WR_ADDR_dma_rw_group_md 112
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/* Register rw_group_md_s, scope dma, type rw */
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typedef struct {
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unsigned int md_s : 16;
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unsigned int dummy1 : 16;
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} reg_dma_rw_group_md_s;
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#define REG_RD_ADDR_dma_rw_group_md_s 116
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#define REG_WR_ADDR_dma_rw_group_md_s 116
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/* Register rw_group_up, scope dma, type rw */
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typedef unsigned int reg_dma_rw_group_up;
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#define REG_RD_ADDR_dma_rw_group_up 120
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#define REG_WR_ADDR_dma_rw_group_up 120
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/* Register rw_group_down, scope dma, type rw */
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typedef unsigned int reg_dma_rw_group_down;
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#define REG_RD_ADDR_dma_rw_group_down 124
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#define REG_WR_ADDR_dma_rw_group_down 124
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/* Register rw_cmd, scope dma, type rw */
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typedef struct {
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unsigned int cont_data : 1;
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unsigned int dummy1 : 31;
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} reg_dma_rw_cmd;
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#define REG_RD_ADDR_dma_rw_cmd 128
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#define REG_WR_ADDR_dma_rw_cmd 128
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/* Register rw_cfg, scope dma, type rw */
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typedef struct {
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unsigned int en : 1;
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unsigned int stop : 1;
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unsigned int dummy1 : 30;
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} reg_dma_rw_cfg;
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#define REG_RD_ADDR_dma_rw_cfg 132
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#define REG_WR_ADDR_dma_rw_cfg 132
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/* Register rw_stat, scope dma, type rw */
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typedef struct {
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unsigned int mode : 5;
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unsigned int list_state : 3;
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unsigned int stream_cmd_src : 8;
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unsigned int dummy1 : 8;
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unsigned int buf : 8;
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} reg_dma_rw_stat;
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#define REG_RD_ADDR_dma_rw_stat 136
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#define REG_WR_ADDR_dma_rw_stat 136
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/* Register rw_intr_mask, scope dma, type rw */
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typedef struct {
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unsigned int group : 1;
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unsigned int ctxt : 1;
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unsigned int data : 1;
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unsigned int in_eop : 1;
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unsigned int stream_cmd : 1;
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unsigned int dummy1 : 27;
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} reg_dma_rw_intr_mask;
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#define REG_RD_ADDR_dma_rw_intr_mask 140
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#define REG_WR_ADDR_dma_rw_intr_mask 140
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/* Register rw_ack_intr, scope dma, type rw */
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typedef struct {
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unsigned int group : 1;
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unsigned int ctxt : 1;
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unsigned int data : 1;
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unsigned int in_eop : 1;
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unsigned int stream_cmd : 1;
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unsigned int dummy1 : 27;
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} reg_dma_rw_ack_intr;
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#define REG_RD_ADDR_dma_rw_ack_intr 144
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#define REG_WR_ADDR_dma_rw_ack_intr 144
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/* Register r_intr, scope dma, type r */
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typedef struct {
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unsigned int group : 1;
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unsigned int ctxt : 1;
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unsigned int data : 1;
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unsigned int in_eop : 1;
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unsigned int stream_cmd : 1;
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unsigned int dummy1 : 27;
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} reg_dma_r_intr;
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#define REG_RD_ADDR_dma_r_intr 148
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/* Register r_masked_intr, scope dma, type r */
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typedef struct {
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unsigned int group : 1;
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unsigned int ctxt : 1;
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unsigned int data : 1;
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unsigned int in_eop : 1;
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unsigned int stream_cmd : 1;
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unsigned int dummy1 : 27;
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} reg_dma_r_masked_intr;
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#define REG_RD_ADDR_dma_r_masked_intr 152
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/* Register rw_stream_cmd, scope dma, type rw */
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typedef struct {
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unsigned int cmd : 10;
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unsigned int dummy1 : 6;
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unsigned int n : 8;
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unsigned int dummy2 : 7;
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unsigned int busy : 1;
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} reg_dma_rw_stream_cmd;
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#define REG_RD_ADDR_dma_rw_stream_cmd 156
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#define REG_WR_ADDR_dma_rw_stream_cmd 156
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/* Constants */
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enum {
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regk_dma_ack_pkt = 0x00000100,
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regk_dma_anytime = 0x00000001,
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regk_dma_array = 0x00000008,
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regk_dma_burst = 0x00000020,
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regk_dma_client = 0x00000002,
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regk_dma_copy_next = 0x00000010,
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regk_dma_copy_up = 0x00000020,
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regk_dma_data_at_eol = 0x00000001,
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regk_dma_dis_c = 0x00000010,
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regk_dma_dis_g = 0x00000020,
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regk_dma_idle = 0x00000001,
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regk_dma_intern = 0x00000004,
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regk_dma_load_c = 0x00000200,
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regk_dma_load_c_n = 0x00000280,
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regk_dma_load_c_next = 0x00000240,
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regk_dma_load_d = 0x00000140,
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regk_dma_load_g = 0x00000300,
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regk_dma_load_g_down = 0x000003c0,
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regk_dma_load_g_next = 0x00000340,
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regk_dma_load_g_up = 0x00000380,
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regk_dma_next_en = 0x00000010,
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regk_dma_next_pkt = 0x00000010,
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regk_dma_no = 0x00000000,
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regk_dma_only_at_wait = 0x00000000,
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regk_dma_restore = 0x00000020,
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regk_dma_rst = 0x00000001,
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regk_dma_running = 0x00000004,
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regk_dma_rw_cfg_default = 0x00000000,
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regk_dma_rw_cmd_default = 0x00000000,
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regk_dma_rw_intr_mask_default = 0x00000000,
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regk_dma_rw_stat_default = 0x00000101,
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regk_dma_rw_stream_cmd_default = 0x00000000,
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regk_dma_save_down = 0x00000020,
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regk_dma_save_up = 0x00000020,
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regk_dma_set_reg = 0x00000050,
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regk_dma_set_w_size1 = 0x00000190,
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regk_dma_set_w_size2 = 0x000001a0,
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regk_dma_set_w_size4 = 0x000001c0,
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regk_dma_stopped = 0x00000002,
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regk_dma_store_c = 0x00000002,
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regk_dma_store_descr = 0x00000000,
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regk_dma_store_g = 0x00000004,
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regk_dma_store_md = 0x00000001,
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regk_dma_sw = 0x00000008,
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regk_dma_update_down = 0x00000020,
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regk_dma_yes = 0x00000001
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};
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#endif /* __dma_defs_h */
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