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656 lines
15 KiB
656 lines
15 KiB
/* Copyright (c) 2012-2018, 2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDSS_H
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#define MDSS_H
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#include <linux/msm_ion.h>
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#include <linux/msm_mdp.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include <linux/irqreturn.h>
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#include <linux/irqdomain.h>
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#include <linux/mdss_io_util.h>
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#include <linux/mdss_smmu_ext.h>
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#include <linux/msm-bus.h>
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#include <linux/file.h>
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#include <linux/dma-direction.h>
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#include <soc/qcom/cx_ipeak.h>
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#include <linux/dma-buf.h>
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#include "mdss_panel.h"
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#define MAX_DRV_SUP_MMB_BLKS 44
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#define MAX_DRV_SUP_PIPES 10
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#define MAX_CLIENT_NAME_LEN 20
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#define MDSS_PINCTRL_STATE_DEFAULT "mdss_default"
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#define MDSS_PINCTRL_STATE_SLEEP "mdss_sleep"
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enum mdss_mdp_clk_type {
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MDSS_CLK_AHB,
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MDSS_CLK_AXI,
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MDSS_CLK_MDP_CORE,
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MDSS_CLK_MDP_LUT,
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MDSS_CLK_MDP_VSYNC,
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MDSS_CLK_MNOC_AHB,
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MDSS_CLK_THROTTLE_AXI,
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MDSS_CLK_BIMC,
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MDSS_MAX_CLK
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};
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enum mdss_iommu_domain_type {
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MDSS_IOMMU_DOMAIN_UNSECURE,
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MDSS_IOMMU_DOMAIN_ROT_UNSECURE,
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MDSS_IOMMU_DOMAIN_SECURE,
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MDSS_IOMMU_DOMAIN_ROT_SECURE,
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MDSS_IOMMU_MAX_DOMAIN
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};
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enum mdss_bus_vote_type {
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VOTE_INDEX_DISABLE,
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VOTE_INDEX_LOW,
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VOTE_INDEX_MID,
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VOTE_INDEX_HIGH,
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VOTE_INDEX_MAX,
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};
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struct mdss_hw_settings {
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char __iomem *reg;
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u32 val;
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};
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struct mdss_max_bw_settings {
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u32 mdss_max_bw_mode;
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u32 mdss_max_bw_val;
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};
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struct mdss_debug_inf {
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void *debug_data;
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void (*debug_enable_clock)(int on);
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};
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struct mdss_perf_tune {
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unsigned long min_mdp_clk;
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u64 min_bus_vote;
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};
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#define MDSS_IRQ_SUSPEND -1
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#define MDSS_IRQ_RESUME 1
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#define MDSS_IRQ_REQ 0
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struct mdss_intr {
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/* requested intr */
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u32 req;
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/* currently enabled intr */
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u32 curr;
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int state;
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spinlock_t lock;
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};
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struct simplified_prefill_factors {
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u32 fmt_mt_nv12_factor;
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u32 fmt_mt_factor;
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u32 fmt_linear_factor;
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u32 scale_factor;
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u32 xtra_ff_factor;
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};
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struct mdss_prefill_data {
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u32 ot_bytes;
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u32 y_buf_bytes;
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u32 y_scaler_lines_bilinear;
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u32 y_scaler_lines_caf;
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u32 post_scaler_pixels;
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u32 pp_pixels;
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u32 fbc_lines;
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u32 ts_threshold;
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u32 ts_end;
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u32 ts_overhead;
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struct mult_factor ts_rate;
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struct simplified_prefill_factors prefill_factors;
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};
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struct mdss_mdp_dsc {
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u32 num;
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char __iomem *base;
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};
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enum mdss_hw_index {
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MDSS_HW_MDP,
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MDSS_HW_DSI0 = 1,
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MDSS_HW_DSI1,
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MDSS_HW_HDMI,
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MDSS_HW_EDP,
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MDSS_HW_MISC,
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MDSS_MAX_HW_BLK
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};
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enum mdss_bus_clients {
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MDSS_MDP_RT,
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MDSS_DSI_RT,
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MDSS_HW_RT,
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MDSS_MDP_NRT,
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MDSS_MAX_BUS_CLIENTS
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};
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struct mdss_pp_block_off {
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u32 sspp_igc_lut_off;
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u32 vig_pcc_off;
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u32 rgb_pcc_off;
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u32 dma_pcc_off;
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u32 lm_pgc_off;
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u32 dspp_gamut_off;
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u32 dspp_pcc_off;
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u32 dspp_pgc_off;
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};
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enum mdss_hw_quirk {
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MDSS_QUIRK_BWCPANIC,
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MDSS_QUIRK_ROTCDP,
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MDSS_QUIRK_DOWNSCALE_HANG,
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MDSS_QUIRK_DSC_RIGHT_ONLY_PU,
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MDSS_QUIRK_DSC_2SLICE_PU_THRPUT,
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MDSS_QUIRK_DMA_BI_DIR,
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MDSS_QUIRK_FMT_PACK_PATTERN,
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MDSS_QUIRK_NEED_SECURE_MAP,
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MDSS_QUIRK_SRC_SPLIT_ALWAYS,
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MDSS_QUIRK_MMSS_GDSC_COLLAPSE,
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MDSS_QUIRK_MDP_CLK_SET_RATE,
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MDSS_QUIRK_HDR_SUPPORT_ENABLED,
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MDSS_QUIRK_MAX,
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};
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enum mdss_hw_capabilities {
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MDSS_CAPS_YUV_CONFIG,
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MDSS_CAPS_SCM_RESTORE_NOT_REQUIRED,
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MDSS_CAPS_3D_MUX_UNDERRUN_RECOVERY_SUPPORTED,
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MDSS_CAPS_MIXER_1_FOR_WB,
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MDSS_CAPS_QSEED3,
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MDSS_CAPS_DEST_SCALER,
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MDSS_CAPS_10_BIT_SUPPORTED,
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MDSS_CAPS_CWB_SUPPORTED,
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MDSS_CAPS_MDP_VOTE_CLK_NOT_SUPPORTED,
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MDSS_CAPS_AVR_SUPPORTED,
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MDSS_CAPS_SEC_DETACH_SMMU,
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MDSS_CAPS_MAX,
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};
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enum mdss_qos_settings {
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MDSS_QOS_PER_PIPE_IB,
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MDSS_QOS_OVERHEAD_FACTOR,
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MDSS_QOS_CDP,
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MDSS_QOS_OTLIM,
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MDSS_QOS_PER_PIPE_LUT,
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MDSS_QOS_SIMPLIFIED_PREFILL,
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MDSS_QOS_VBLANK_PANIC_CTRL,
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MDSS_QOS_TS_PREFILL,
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MDSS_QOS_REMAPPER,
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MDSS_QOS_IB_NOCR,
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MDSS_QOS_WB2_WRITE_GATHER_EN,
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MDSS_QOS_WB_QOS,
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MDSS_QOS_MAX,
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};
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enum mdss_mdp_pipe_type {
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MDSS_MDP_PIPE_TYPE_INVALID = -1,
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MDSS_MDP_PIPE_TYPE_VIG = 0,
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MDSS_MDP_PIPE_TYPE_RGB,
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MDSS_MDP_PIPE_TYPE_DMA,
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MDSS_MDP_PIPE_TYPE_CURSOR,
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MDSS_MDP_PIPE_TYPE_MAX,
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};
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enum mdss_mdp_intf_index {
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MDSS_MDP_NO_INTF,
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MDSS_MDP_INTF0,
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MDSS_MDP_INTF1,
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MDSS_MDP_INTF2,
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MDSS_MDP_INTF3,
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MDSS_MDP_MAX_INTF
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};
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struct reg_bus_client {
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char name[MAX_CLIENT_NAME_LEN];
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short usecase_ndx;
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u32 id;
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struct list_head list;
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};
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struct mdss_smmu_client {
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struct mdss_smmu_intf base;
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struct dma_iommu_mapping *mmu_mapping;
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struct dss_module_power mp;
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struct reg_bus_client *reg_bus_clt;
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bool domain_attached;
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bool domain_reattach;
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bool handoff_pending;
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void __iomem *mmu_base;
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struct list_head _client;
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};
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struct mdss_mdp_qseed3_lut_tbl {
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bool valid;
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u32 *dir_lut;
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u32 *cir_lut;
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u32 *sep_lut;
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};
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struct mdss_scaler_block {
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u32 vig_scaler_off;
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u32 vig_scaler_lut_off;
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u32 has_dest_scaler;
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char __iomem *dest_base;
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u32 ndest_scalers;
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u32 *dest_scaler_off;
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u32 *dest_scaler_lut_off;
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struct mdss_mdp_qseed3_lut_tbl lut_tbl;
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/*
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* Lock is mainly to serialize access to LUT.
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* LUT values come asynchronously from userspace
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* via ioctl.
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*/
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struct mutex scaler_lock;
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};
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struct mdss_data_type;
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struct mdss_smmu_ops {
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int (*smmu_attach)(struct mdss_data_type *mdata);
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int (*smmu_detach)(struct mdss_data_type *mdata);
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int (*smmu_get_domain_id)(u32 type);
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struct dma_buf_attachment * (*smmu_dma_buf_attach)(
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struct dma_buf *dma_buf, struct device *devce,
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int domain);
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int (*smmu_map_dma_buf)(struct dma_buf *dma_buf,
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struct sg_table *table, int domain,
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dma_addr_t *iova, unsigned long *size, int dir);
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void (*smmu_unmap_dma_buf)(struct sg_table *table, int domain,
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int dir, struct dma_buf *dma_buf);
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int (*smmu_dma_alloc_coherent)(struct device *dev, size_t size,
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dma_addr_t *phys, dma_addr_t *iova, void **cpu_addr,
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gfp_t gfp, int domain);
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void (*smmu_dma_free_coherent)(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t phys, dma_addr_t iova,
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int domain);
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int (*smmu_map)(int domain, phys_addr_t iova, phys_addr_t phys, int
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gfp_order, int prot);
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void (*smmu_unmap)(int domain, unsigned long iova, int gfp_order);
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char * (*smmu_dsi_alloc_buf)(struct device *dev, int size,
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dma_addr_t *dmap, gfp_t gfp);
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int (*smmu_dsi_map_buffer)(phys_addr_t phys, unsigned int domain,
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unsigned long size, dma_addr_t *dma_addr,
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void *cpu_addr, int dir);
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void (*smmu_dsi_unmap_buffer)(dma_addr_t dma_addr, int domain,
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unsigned long size, int dir);
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void (*smmu_deinit)(struct mdss_data_type *mdata);
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};
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struct mdss_data_type {
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u32 mdp_rev;
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struct clk *mdp_clk[MDSS_MAX_CLK];
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struct regulator *fs;
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struct regulator *core_gdsc;
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struct regulator *vdd_cx;
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u32 vdd_cx_min_uv;
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u32 vdd_cx_max_uv;
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bool batfet_required;
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struct regulator *batfet;
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bool en_svs_high;
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u32 max_mdp_clk_rate;
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struct mdss_util_intf *mdss_util;
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unsigned long mdp_clk_rate;
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struct platform_device *pdev;
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struct dss_io_data mdss_io;
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struct dss_io_data vbif_io;
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struct dss_io_data vbif_nrt_io;
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char __iomem *mdp_base;
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struct mdss_smmu_client mdss_smmu[MDSS_IOMMU_MAX_DOMAIN];
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struct mdss_smmu_ops smmu_ops;
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struct mutex reg_lock;
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/* bitmap to track pipes that have BWC enabled */
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DECLARE_BITMAP(bwc_enable_map, MAX_DRV_SUP_PIPES);
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/* bitmap to track hw workarounds */
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DECLARE_BITMAP(mdss_quirk_map, MDSS_QUIRK_MAX);
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/* bitmap to track total mmbs in use */
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DECLARE_BITMAP(mmb_alloc_map, MAX_DRV_SUP_MMB_BLKS);
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/* bitmap to track qos applicable settings */
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DECLARE_BITMAP(mdss_qos_map, MDSS_QOS_MAX);
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/* bitmap to track hw capabilities/features */
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DECLARE_BITMAP(mdss_caps_map, MDSS_CAPS_MAX);
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u32 has_bwc;
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/* values used when HW has a common panic/robust LUT */
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u32 default_panic_lut0;
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u32 default_panic_lut1;
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u32 default_robust_lut;
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/* values used when HW has panic/robust LUTs per pipe */
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u32 default_panic_lut_per_pipe_linear;
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u32 default_panic_lut_per_pipe_tile;
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u32 default_robust_lut_per_pipe_linear;
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u32 default_robust_lut_per_pipe_tile;
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u32 has_decimation;
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bool has_fixed_qos_arbiter_enabled;
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bool has_panic_ctrl;
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u32 wfd_mode;
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u32 has_no_lut_read;
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atomic_t sd_client_count;
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atomic_t sc_client_count;
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u8 has_wb_ad;
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u8 has_non_scalar_rgb;
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bool has_src_split;
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bool idle_pc_enabled;
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bool has_pingpong_split;
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bool has_pixel_ram;
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bool needs_hist_vote;
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bool has_ubwc;
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bool has_wb_ubwc;
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bool has_separate_rotator;
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u32 default_ot_rd_limit;
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u32 default_ot_wr_limit;
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struct irq_domain *irq_domain;
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u32 *mdp_irq_raw;
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u32 *mdp_irq_export;
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u32 *mdp_irq_mask;
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u32 mdp_hist_irq_mask;
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u32 mdp_intf_irq_mask;
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int suspend_fs_ena;
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u8 clk_ena;
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u8 fs_ena;
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u8 vsync_ena;
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struct notifier_block gdsc_cb;
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u32 res_init;
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u32 highest_bank_bit;
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u32 smp_mb_cnt;
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u32 smp_mb_size;
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u32 smp_mb_per_pipe;
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u32 pixel_ram_size;
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u32 rot_block_size;
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/* HW RT bus (AXI) */
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u32 hw_rt_bus_hdl;
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u32 hw_rt_bus_ref_cnt;
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/* data bus (AXI) */
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u32 bus_hdl;
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u32 bus_ref_cnt;
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struct mutex bus_lock;
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/* register bus (AHB) */
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u32 reg_bus_hdl;
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u32 reg_bus_usecase_ndx;
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struct list_head reg_bus_clist;
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struct mutex reg_bus_lock;
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struct reg_bus_client *reg_bus_clt;
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struct reg_bus_client *pp_reg_bus_clt;
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u32 axi_port_cnt;
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u32 nrt_axi_port_cnt;
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u32 bus_channels;
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u32 curr_bw_uc_idx;
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u32 ao_bw_uc_idx; /* active only idx */
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struct msm_bus_scale_pdata *bus_scale_table;
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struct msm_bus_scale_pdata *reg_bus_scale_table;
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struct msm_bus_scale_pdata *hw_rt_bus_scale_table;
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u32 max_bw_low;
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u32 max_bw_high;
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u32 max_bw_per_pipe;
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u32 *vbif_rt_qos;
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u32 *vbif_nrt_qos;
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u32 npriority_lvl;
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struct mult_factor ab_factor;
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struct mult_factor ib_factor;
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struct mult_factor ib_factor_overlap;
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struct mult_factor clk_factor;
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struct mult_factor per_pipe_ib_factor;
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bool apply_post_scale_bytes;
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bool hflip_buffer_reused;
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u32 disable_prefill;
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u32 *clock_levels;
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u32 nclk_lvl;
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u32 enable_gate;
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u32 enable_bw_release;
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u32 enable_rotator_bw_release;
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u32 enable_cdp;
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u32 serialize_wait4pp;
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u32 wait4autorefresh;
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u32 lines_before_active;
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struct mdss_hw_settings *hw_settings;
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int rects_per_sspp[MDSS_MDP_PIPE_TYPE_MAX];
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struct mdss_mdp_pipe *vig_pipes;
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struct mdss_mdp_pipe *rgb_pipes;
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struct mdss_mdp_pipe *dma_pipes;
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struct mdss_mdp_pipe *cursor_pipes;
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u32 nvig_pipes;
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u32 nrgb_pipes;
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u32 ndma_pipes;
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u32 max_target_zorder;
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u8 ncursor_pipes;
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u32 max_cursor_size;
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u32 nppb_ctl;
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u32 *ppb_ctl;
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u32 nppb_cfg;
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u32 *ppb_cfg;
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char __iomem *slave_pingpong_base;
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struct mdss_mdp_mixer *mixer_intf;
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struct mdss_mdp_mixer *mixer_wb;
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u32 nmixers_intf;
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u32 nmixers_wb;
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u32 max_mixer_width;
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u32 max_pipe_width;
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struct mdss_mdp_writeback *wb;
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u32 nwb;
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u32 *wb_offsets;
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u32 nwb_offsets;
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struct mutex wb_lock;
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struct mdss_mdp_ctl *ctl_off;
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u32 nctl;
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u32 ndspp;
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struct mdss_mdp_dp_intf *dp_off;
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u32 ndp;
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void *video_intf;
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u32 nintf;
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struct mdss_mdp_ad *ad_off;
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struct mdss_ad_info *ad_cfgs;
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u32 nad_cfgs;
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u32 nmax_concurrent_ad_hw;
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struct workqueue_struct *ad_calc_wq;
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u32 ad_debugen;
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|
bool mem_retain;
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|
|
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struct mdss_intr hist_intr;
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|
|
|
int iommu_attached;
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|
|
|
u32 dbg_bus_flags;
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struct debug_bus *dbg_bus;
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u32 dbg_bus_size;
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struct vbif_debug_bus *vbif_dbg_bus;
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u32 vbif_dbg_bus_size;
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struct vbif_debug_bus *nrt_vbif_dbg_bus;
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u32 nrt_vbif_dbg_bus_size;
|
|
struct mdss_debug_inf debug_inf;
|
|
bool mixer_switched;
|
|
struct mdss_panel_cfg pan_cfg;
|
|
struct mdss_prefill_data prefill_data;
|
|
u32 min_prefill_lines; /* this changes within different chipsets */
|
|
u32 props;
|
|
|
|
bool twm_en;
|
|
int handoff_pending;
|
|
bool idle_pc;
|
|
struct mdss_perf_tune perf_tune;
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|
bool traffic_shaper_en;
|
|
int iommu_ref_cnt;
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|
u32 latency_buff_per;
|
|
atomic_t active_intf_cnt;
|
|
bool has_rot_dwnscale;
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|
bool regulator_notif_register;
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|
|
|
u64 ab[MDSS_MAX_BUS_CLIENTS];
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|
u64 ib[MDSS_MAX_BUS_CLIENTS];
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|
struct mdss_pp_block_off pp_block_off;
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|
|
|
struct mdss_mdp_cdm *cdm_off;
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|
u32 ncdm;
|
|
struct mutex cdm_lock;
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|
|
|
struct mdss_mdp_dsc *dsc_off;
|
|
u32 ndsc;
|
|
|
|
struct mdss_max_bw_settings *max_bw_settings;
|
|
u32 bw_mode_bitmap;
|
|
u32 max_bw_settings_cnt;
|
|
bool bw_limit_pending;
|
|
|
|
struct mdss_max_bw_settings *max_per_pipe_bw_settings;
|
|
u32 mdss_per_pipe_bw_cnt;
|
|
u32 min_bw_per_pipe;
|
|
|
|
u32 bcolor0;
|
|
u32 bcolor1;
|
|
u32 bcolor2;
|
|
struct mdss_scaler_block *scaler_off;
|
|
|
|
u32 max_dest_scaler_input_width;
|
|
u32 max_dest_scaler_output_width;
|
|
struct mdss_mdp_destination_scaler *ds;
|
|
u32 sec_disp_en;
|
|
u32 sec_cam_en;
|
|
u32 sec_session_cnt;
|
|
wait_queue_head_t secure_waitq;
|
|
struct cx_ipeak_client *mdss_cx_ipeak;
|
|
struct mult_factor bus_throughput_factor;
|
|
};
|
|
|
|
extern struct mdss_data_type *mdss_res;
|
|
|
|
struct irq_info {
|
|
u32 irq;
|
|
u32 irq_mask;
|
|
u32 irq_wake_mask;
|
|
u32 irq_ena;
|
|
u32 irq_wake_ena;
|
|
u32 irq_buzy;
|
|
};
|
|
|
|
struct mdss_hw {
|
|
u32 hw_ndx;
|
|
void *ptr;
|
|
struct irq_info *irq_info;
|
|
irqreturn_t (*irq_handler)(int irq, void *ptr);
|
|
};
|
|
|
|
struct irq_info *mdss_intr_line(void);
|
|
void mdss_bus_bandwidth_ctrl(int enable);
|
|
int mdss_iommu_ctrl(int enable);
|
|
int mdss_bus_scale_set_quota(int client, u64 ab_quota, u64 ib_quota);
|
|
int mdss_update_reg_bus_vote(struct reg_bus_client *bus_client,
|
|
u32 usecase_ndx);
|
|
struct reg_bus_client *mdss_reg_bus_vote_client_create(char *client_name);
|
|
void mdss_reg_bus_vote_client_destroy(struct reg_bus_client *bus_client);
|
|
|
|
struct mdss_util_intf {
|
|
bool mdp_probe_done;
|
|
int (*register_irq)(struct mdss_hw *hw);
|
|
void (*enable_irq)(struct mdss_hw *hw);
|
|
void (*disable_irq)(struct mdss_hw *hw);
|
|
void (*enable_wake_irq)(struct mdss_hw *hw);
|
|
void (*disable_wake_irq)(struct mdss_hw *hw);
|
|
void (*disable_irq_nosync)(struct mdss_hw *hw);
|
|
int (*irq_dispatch)(u32 hw_ndx, int irq, void *ptr);
|
|
int (*get_iommu_domain)(u32 type);
|
|
int (*iommu_attached)(void);
|
|
int (*iommu_ctrl)(int enable);
|
|
void (*iommu_lock)(void);
|
|
void (*iommu_unlock)(void);
|
|
void (*vbif_reg_lock)(void);
|
|
void (*vbif_reg_unlock)(void);
|
|
int (*secure_session_ctrl)(int enable);
|
|
void (*bus_bandwidth_ctrl)(int enable);
|
|
int (*bus_scale_set_quota)(int client, u64 ab_quota, u64 ib_quota);
|
|
int (*panel_intf_status)(u32 disp_num, u32 intf_type);
|
|
struct mdss_panel_cfg* (*panel_intf_type)(int intf_val);
|
|
int (*dyn_clk_gating_ctrl)(int enable);
|
|
bool (*mdp_handoff_pending)(void);
|
|
};
|
|
|
|
struct mdss_util_intf *mdss_get_util_intf(void);
|
|
bool mdss_get_irq_enable_state(struct mdss_hw *hw);
|
|
|
|
static inline int mdss_get_sd_client_cnt(void)
|
|
{
|
|
if (!mdss_res)
|
|
return 0;
|
|
else
|
|
return atomic_read(&mdss_res->sd_client_count);
|
|
}
|
|
|
|
static inline int mdss_get_sc_client_cnt(void)
|
|
{
|
|
if (!mdss_res)
|
|
return 0;
|
|
else
|
|
return atomic_read(&mdss_res->sc_client_count);
|
|
}
|
|
|
|
static inline void mdss_set_quirk(struct mdss_data_type *mdata,
|
|
enum mdss_hw_quirk bit)
|
|
{
|
|
set_bit(bit, mdata->mdss_quirk_map);
|
|
}
|
|
|
|
static inline bool mdss_has_quirk(struct mdss_data_type *mdata,
|
|
enum mdss_hw_quirk bit)
|
|
{
|
|
return test_bit(bit, mdata->mdss_quirk_map);
|
|
}
|
|
|
|
#define MDSS_VBIF_WRITE(mdata, offset, value, nrt_vbif) \
|
|
(nrt_vbif ? dss_reg_w(&mdata->vbif_nrt_io, offset, value, 0) :\
|
|
dss_reg_w(&mdata->vbif_io, offset, value, 0))
|
|
#define MDSS_VBIF_READ(mdata, offset, nrt_vbif) \
|
|
(nrt_vbif ? dss_reg_r(&mdata->vbif_nrt_io, offset, 0) :\
|
|
dss_reg_r(&mdata->vbif_io, offset, 0))
|
|
#define MDSS_REG_WRITE(mdata, offset, value) \
|
|
dss_reg_w(&mdata->mdss_io, offset, value, 0)
|
|
#define MDSS_REG_READ(mdata, offset) \
|
|
dss_reg_r(&mdata->mdss_io, offset, 0)
|
|
|
|
#endif /* MDSS_H */
|
|
|