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192 lines
6.1 KiB
192 lines
6.1 KiB
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#if !defined(_GSI_EMULATION_H_)
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# define _GSI_EMULATION_H_
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# include <linux/interrupt.h>
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# include "gsi.h"
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# include "gsi_reg.h"
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# include "gsi_emulation_stubs.h"
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# define gsi_emu_readl(c) (readl(c))
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# define gsi_emu_writel(v, c) ({ __iowmb(); writel_relaxed((v), (c)); })
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# define CNTRLR_BASE 0
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/*
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* The following file contains definitions and declarations that are
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* germane only to the IPA emulation system, which is run from an X86
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* environment. Declaration's for non-X86 (ie. arm) are merely stubs
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* to facilitate compile and link.
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*
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* Interrupt controller registers.
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* Descriptions taken from the EMULATION interrupt controller SWI.
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* - There is only one Master Enable register
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* - Each group of 32 interrupt lines (range) is controlled by 8 registers,
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* which are consecutive in memory:
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* GE_INT_ENABLE_n
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* GE_INT_ENABLE_CLEAR_n
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* GE_INT_ENABLE_SET_n
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* GE_INT_TYPE_n
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* GE_IRQ_STATUS_n
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* GE_RAW_STATUS_n
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* GE_INT_CLEAR_n
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* GE_SOFT_INT_n
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* - After the above 8 registers, there are the registers of the next
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* group (range) of 32 interrupt lines, and so on.
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*/
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/** @brief The interrupt controller version and interrupt count register.
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* Specifies interrupt controller version (upper 16 bits) and the
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* number of interrupt lines supported by HW (lower 16 bits).
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*/
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# define GE_INT_CTL_VER_CNT \
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(CNTRLR_BASE + 0x0000)
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/** @brief Enable or disable physical IRQ output signal to the system,
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* not affecting any status registers.
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*
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* 0x0 : DISABLE IRQ output disabled
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* 0x1 : ENABLE IRQ output enabled
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*/
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# define GE_INT_OUT_ENABLE \
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(CNTRLR_BASE + 0x0004)
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/** @brief The IRQ master enable register.
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* Bit #0: IRQ_ENABLE, set 0 to disable, 1 to enable.
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*/
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# define GE_INT_MASTER_ENABLE \
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(CNTRLR_BASE + 0x0008)
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# define GE_INT_MASTER_STATUS \
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(CNTRLR_BASE + 0x000C)
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/** @brief Each bit disables (bit=0, default) or enables (bit=1) the
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* corresponding interrupt source
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*/
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# define GE_INT_ENABLE_n(n) \
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(CNTRLR_BASE + 0x0010 + 0x20 * (n))
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/** @brief Write bit=1 to clear (to 0) the corresponding bit(s) in INT_ENABLE.
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* Does nothing for bit=0
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*/
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# define GE_INT_ENABLE_CLEAR_n(n) \
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(CNTRLR_BASE + 0x0014 + 0x20 * (n))
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/** @brief Write bit=1 to set (to 1) the corresponding bit(s) in INT_ENABLE.
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* Does nothing for bit=0
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*/
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# define GE_INT_ENABLE_SET_n(n) \
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(CNTRLR_BASE + 0x0018 + 0x20 * (n))
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/** @brief Select level (bit=0, default) or edge (bit=1) sensitive input
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* detection logic for each corresponding interrupt source
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*/
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# define GE_INT_TYPE_n(n) \
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(CNTRLR_BASE + 0x001C + 0x20 * (n))
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/** @brief Shows the interrupt sources captured in RAW_STATUS that have been
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* steered to irq_n by INT_SELECT. Interrupts must also be enabled by
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* INT_ENABLE and MASTER_ENABLE. Read only register.
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* Bit values: 1=active, 0=inactive
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*/
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# define GE_IRQ_STATUS_n(n) \
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(CNTRLR_BASE + 0x0020 + 0x20 * (n))
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/** @brief Shows the interrupt sources that have been latched by the input
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* logic of the Interrupt Controller. Read only register.
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* Bit values: 1=active, 0=inactive
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*/
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# define GE_RAW_STATUS_n(n) \
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(CNTRLR_BASE + 0x0024 + 0x20 * (n))
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/** @brief Write bit=1 to clear the corresponding bit(s) in RAW_STATUS.
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* Does nothing for bit=0
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*/
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# define GE_INT_CLEAR_n(n) \
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(CNTRLR_BASE + 0x0028 + 0x20 * (n))
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/** @brief Write bit=1 to set the corresponding bit(s) in RAW_STATUS.
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* Does nothing for bit=0.
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* @note Only functional for edge detected interrupts
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*/
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# define GE_SOFT_INT_n(n) \
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(CNTRLR_BASE + 0x002C + 0x20 * (n))
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/** @brief Maximal number of ranges in SW. Each range supports 32 interrupt
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* lines. If HW is extended considerably, increase this value
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*/
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# define DEO_IC_MAX_RANGE_CNT 8
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/** @brief Size of the registers of one range in memory, in bytes */
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# define DEO_IC_RANGE_MEM_SIZE 32 /* SWI: 8 registers, no gaps */
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/** @brief Minimal Interrupt controller HW version */
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# define DEO_IC_INT_CTL_VER_MIN 0x0102
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#if defined(CONFIG_IPA_EMULATION) /* declarations to follow */
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/*
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* *****************************************************************************
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* The following used to set up the EMULATION interrupt controller...
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* *****************************************************************************
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*/
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int setup_emulator_cntrlr(
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void __iomem *intcntrlr_base,
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u32 intcntrlr_mem_size);
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/*
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* *****************************************************************************
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* The following for EMULATION hard irq...
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* *****************************************************************************
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*/
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irqreturn_t emulator_hard_irq_isr(
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int irq,
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void *ctxt);
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/*
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* *****************************************************************************
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* The following for EMULATION soft irq...
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* *****************************************************************************
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*/
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irqreturn_t emulator_soft_irq_isr(
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int irq,
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void *ctxt);
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# else /* #if !defined(CONFIG_IPA_EMULATION) then definitions to follow */
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static inline int setup_emulator_cntrlr(
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void __iomem *intcntrlr_base,
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u32 intcntrlr_mem_size)
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{
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return 0;
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}
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static inline irqreturn_t emulator_hard_irq_isr(
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int irq,
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void *ctxt)
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{
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return IRQ_NONE;
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}
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static inline irqreturn_t emulator_soft_irq_isr(
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int irq,
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void *ctxt)
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{
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return IRQ_HANDLED;
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}
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# endif /* #if defined(CONFIG_IPA_EMULATION) */
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#endif /* #if !defined(_GSI_EMULATION_H_) */
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