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314 lines
8.3 KiB
314 lines
8.3 KiB
/*******************************************************************************
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STMMAC Ethernet Driver -- MDIO bus implementation
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Provides Bus interface for MII registers
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Carl Shaw <carl.shaw@st.com>
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Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mii.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/of_mdio.h>
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#include <linux/phy.h>
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#include <linux/slab.h>
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#include "stmmac.h"
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#define MII_BUSY 0x00000001
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#define MII_WRITE 0x00000002
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/* GMAC4 defines */
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#define MII_GMAC4_GOC_SHIFT 2
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#define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
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#define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
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/**
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* stmmac_mdio_read
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* @bus: points to the mii_bus structure
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* @phyaddr: MII addr
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* @phyreg: MII reg
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* Description: it reads data from the MII register from within the phy device.
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* For the 7111 GMAC, we must set the bit 0 in the MII address register while
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* accessing the PHY registers.
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* Fortunately, it seems this has no drawback for the 7109 MAC.
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*/
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static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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{
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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u32 v;
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int data;
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u32 value = MII_BUSY;
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value |= (phyaddr << priv->hw->mii.addr_shift)
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& priv->hw->mii.addr_mask;
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value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
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value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
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& priv->hw->mii.clk_csr_mask;
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if (priv->plat->has_gmac4)
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value |= MII_GMAC4_READ;
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if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000))
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return -EBUSY;
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writel(value, priv->ioaddr + mii_address);
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if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000))
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return -EBUSY;
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/* Read the data from the MII data register */
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data = (int)readl(priv->ioaddr + mii_data);
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return data;
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}
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/**
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* stmmac_mdio_write
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* @bus: points to the mii_bus structure
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* @phyaddr: MII addr
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* @phyreg: MII reg
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* @phydata: phy data
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* Description: it writes the data into the MII register from within the device.
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*/
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static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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u16 phydata)
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{
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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u32 v;
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u32 value = MII_BUSY;
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value |= (phyaddr << priv->hw->mii.addr_shift)
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& priv->hw->mii.addr_mask;
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value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
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value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
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& priv->hw->mii.clk_csr_mask;
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if (priv->plat->has_gmac4)
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value |= MII_GMAC4_WRITE;
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else
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value |= MII_WRITE;
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000))
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return -EBUSY;
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/* Set the MII address register to write */
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writel(phydata, priv->ioaddr + mii_data);
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writel(value, priv->ioaddr + mii_address);
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/* Wait until any existing MII operation is complete */
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return readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000);
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}
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/**
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* stmmac_mdio_reset
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* @bus: points to the mii_bus structure
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* Description: reset the MII bus
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*/
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int stmmac_mdio_reset(struct mii_bus *bus)
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{
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#if IS_ENABLED(CONFIG_STMMAC_PLATFORM)
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data;
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#ifdef CONFIG_OF
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if (priv->device->of_node) {
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if (data->reset_gpio < 0) {
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struct device_node *np = priv->device->of_node;
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if (!np)
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return 0;
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data->reset_gpio = of_get_named_gpio(np,
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"snps,reset-gpio", 0);
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if (data->reset_gpio < 0)
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return 0;
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data->active_low = of_property_read_bool(np,
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"snps,reset-active-low");
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of_property_read_u32_array(np,
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"snps,reset-delays-us", data->delays, 3);
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if (devm_gpio_request(priv->device, data->reset_gpio,
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"mdio-reset"))
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return 0;
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}
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gpio_direction_output(data->reset_gpio,
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data->active_low ? 1 : 0);
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if (data->delays[0])
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msleep(DIV_ROUND_UP(data->delays[0], 1000));
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gpio_set_value(data->reset_gpio, data->active_low ? 0 : 1);
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if (data->delays[1])
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msleep(DIV_ROUND_UP(data->delays[1], 1000));
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gpio_set_value(data->reset_gpio, data->active_low ? 1 : 0);
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if (data->delays[2])
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msleep(DIV_ROUND_UP(data->delays[2], 1000));
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}
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#endif
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if (data->phy_reset) {
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netdev_dbg(ndev, "stmmac_mdio_reset: calling phy_reset\n");
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data->phy_reset(priv->plat->bsp_priv);
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}
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/* This is a workaround for problems with the STE101P PHY.
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* It doesn't complete its reset until at least one clock cycle
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* on MDC, so perform a dummy mdio read. To be updated for GMAC4
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* if needed.
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*/
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if (!priv->plat->has_gmac4)
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writel(0, priv->ioaddr + mii_address);
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#endif
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return 0;
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}
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/**
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* stmmac_mdio_register
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* @ndev: net device structure
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* Description: it registers the MII bus
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*/
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int stmmac_mdio_register(struct net_device *ndev)
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{
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int err = 0;
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struct mii_bus *new_bus;
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struct stmmac_priv *priv = netdev_priv(ndev);
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struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
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struct device_node *mdio_node = priv->plat->mdio_node;
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struct device *dev = ndev->dev.parent;
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int addr, found;
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if (!mdio_bus_data)
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return 0;
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new_bus = mdiobus_alloc();
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if (!new_bus)
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return -ENOMEM;
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if (mdio_bus_data->irqs)
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memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
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#ifdef CONFIG_OF
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if (priv->device->of_node)
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mdio_bus_data->reset_gpio = -1;
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#endif
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new_bus->name = "stmmac";
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new_bus->read = &stmmac_mdio_read;
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new_bus->write = &stmmac_mdio_write;
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new_bus->reset = &stmmac_mdio_reset;
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snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
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new_bus->name, priv->plat->bus_id);
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new_bus->priv = ndev;
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new_bus->phy_mask = mdio_bus_data->phy_mask;
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new_bus->parent = priv->device;
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if (mdio_node)
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err = of_mdiobus_register(new_bus, mdio_node);
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else
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err = mdiobus_register(new_bus);
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if (err != 0) {
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dev_err(dev, "Cannot register the MDIO bus\n");
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goto bus_register_fail;
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}
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if (priv->plat->phy_node || mdio_node)
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goto bus_register_done;
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found = 0;
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for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
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struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
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if (!phydev || phydev->phy_id == 0xffff)
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continue;
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/*
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* If an IRQ was provided to be assigned after
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* the bus probe, do it here.
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*/
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if (!mdio_bus_data->irqs &&
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(mdio_bus_data->probed_phy_irq > 0)) {
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new_bus->irq[addr] = mdio_bus_data->probed_phy_irq;
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phydev->irq = mdio_bus_data->probed_phy_irq;
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}
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/*
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* If we're going to bind the MAC to this PHY bus,
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* and no PHY number was provided to the MAC,
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* use the one probed here.
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*/
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if (priv->plat->phy_addr == -1)
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priv->plat->phy_addr = addr;
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priv->phydev = phydev;
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phy_attached_info(phydev);
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found = 1;
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}
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if (!found && !mdio_node) {
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dev_warn(dev, "No PHY found\n");
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mdiobus_unregister(new_bus);
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mdiobus_free(new_bus);
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return -ENODEV;
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}
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bus_register_done:
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priv->mii = new_bus;
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return 0;
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bus_register_fail:
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mdiobus_free(new_bus);
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return err;
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}
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/**
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* stmmac_mdio_unregister
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* @ndev: net device structure
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* Description: it unregisters the MII bus
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*/
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int stmmac_mdio_unregister(struct net_device *ndev)
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{
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struct stmmac_priv *priv = netdev_priv(ndev);
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if (!priv->mii)
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return 0;
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mdiobus_unregister(priv->mii);
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priv->mii->priv = NULL;
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mdiobus_free(priv->mii);
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priv->mii = NULL;
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return 0;
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}
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