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461 lines
12 KiB
461 lines
12 KiB
/*
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* Copyright © 2016-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "i915_drv.h"
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#include "intel_guc_ct.h"
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enum { CTB_SEND = 0, CTB_RECV = 1 };
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enum { CTB_OWNER_HOST = 0 };
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void intel_guc_ct_init_early(struct intel_guc_ct *ct)
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{
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/* we're using static channel owners */
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ct->host_channel.owner = CTB_OWNER_HOST;
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}
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static inline const char *guc_ct_buffer_type_to_str(u32 type)
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{
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switch (type) {
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case INTEL_GUC_CT_BUFFER_TYPE_SEND:
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return "SEND";
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case INTEL_GUC_CT_BUFFER_TYPE_RECV:
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return "RECV";
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default:
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return "<invalid>";
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}
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}
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static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc,
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u32 cmds_addr, u32 size, u32 owner)
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{
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DRM_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n",
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desc, cmds_addr, size, owner);
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memset(desc, 0, sizeof(*desc));
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desc->addr = cmds_addr;
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desc->size = size;
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desc->owner = owner;
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}
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static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
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{
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DRM_DEBUG_DRIVER("CT: desc %p reset head=%u tail=%u\n",
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desc, desc->head, desc->tail);
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desc->head = 0;
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desc->tail = 0;
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desc->is_in_error = 0;
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}
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static int guc_action_register_ct_buffer(struct intel_guc *guc,
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u32 desc_addr,
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u32 type)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER,
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desc_addr,
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sizeof(struct guc_ct_buffer_desc),
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type
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};
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int err;
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/* Can't use generic send(), CT registration must go over MMIO */
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err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action));
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if (err)
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DRM_ERROR("CT: register %s buffer failed; err=%d\n",
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guc_ct_buffer_type_to_str(type), err);
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return err;
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}
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static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
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u32 owner,
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u32 type)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER,
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owner,
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type
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};
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int err;
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/* Can't use generic send(), CT deregistration must go over MMIO */
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err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action));
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if (err)
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DRM_ERROR("CT: deregister %s buffer failed; owner=%d err=%d\n",
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guc_ct_buffer_type_to_str(type), owner, err);
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return err;
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}
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static bool ctch_is_open(struct intel_guc_ct_channel *ctch)
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{
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return ctch->vma != NULL;
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}
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static int ctch_init(struct intel_guc *guc,
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struct intel_guc_ct_channel *ctch)
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{
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struct i915_vma *vma;
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void *blob;
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int err;
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int i;
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GEM_BUG_ON(ctch->vma);
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/* We allocate 1 page to hold both descriptors and both buffers.
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* ___________.....................
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* |desc (SEND)| :
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* |___________| PAGE/4
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* :___________....................:
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* |desc (RECV)| :
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* |___________| PAGE/4
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* :_______________________________:
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* |cmds (SEND) |
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* | PAGE/4
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* |_______________________________|
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* |cmds (RECV) |
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* | PAGE/4
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* |_______________________________|
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*
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* Each message can use a maximum of 32 dwords and we don't expect to
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* have more than 1 in flight at any time, so we have enough space.
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* Some logic further ahead will rely on the fact that there is only 1
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* page and that it is always mapped, so if the size is changed the
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* other code will need updating as well.
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*/
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/* allocate vma */
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vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_out;
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}
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ctch->vma = vma;
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/* map first page */
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blob = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
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if (IS_ERR(blob)) {
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err = PTR_ERR(blob);
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goto err_vma;
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}
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DRM_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma));
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/* store pointers to desc and cmds */
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for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
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GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
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ctch->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
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ctch->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
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}
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return 0;
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err_vma:
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i915_vma_unpin_and_release(&ctch->vma);
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err_out:
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DRM_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n",
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ctch->owner, err);
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return err;
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}
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static void ctch_fini(struct intel_guc *guc,
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struct intel_guc_ct_channel *ctch)
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{
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GEM_BUG_ON(!ctch->vma);
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i915_gem_object_unpin_map(ctch->vma->obj);
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i915_vma_unpin_and_release(&ctch->vma);
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}
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static int ctch_open(struct intel_guc *guc,
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struct intel_guc_ct_channel *ctch)
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{
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u32 base;
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int err;
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int i;
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DRM_DEBUG_DRIVER("CT: channel %d reopen=%s\n",
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ctch->owner, yesno(ctch_is_open(ctch)));
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if (!ctch->vma) {
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err = ctch_init(guc, ctch);
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if (unlikely(err))
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goto err_out;
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}
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/* vma should be already allocated and map'ed */
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base = guc_ggtt_offset(ctch->vma);
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/* (re)initialize descriptors
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* cmds buffers are in the second half of the blob page
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*/
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for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
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GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
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guc_ct_buffer_desc_init(ctch->ctbs[i].desc,
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base + PAGE_SIZE/4 * i + PAGE_SIZE/2,
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PAGE_SIZE/4,
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ctch->owner);
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}
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/* register buffers, starting wirh RECV buffer
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* descriptors are in first half of the blob
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*/
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err = guc_action_register_ct_buffer(guc,
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base + PAGE_SIZE/4 * CTB_RECV,
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INTEL_GUC_CT_BUFFER_TYPE_RECV);
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if (unlikely(err))
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goto err_fini;
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err = guc_action_register_ct_buffer(guc,
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base + PAGE_SIZE/4 * CTB_SEND,
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INTEL_GUC_CT_BUFFER_TYPE_SEND);
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if (unlikely(err))
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goto err_deregister;
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return 0;
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err_deregister:
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guc_action_deregister_ct_buffer(guc,
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ctch->owner,
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INTEL_GUC_CT_BUFFER_TYPE_RECV);
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err_fini:
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ctch_fini(guc, ctch);
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err_out:
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DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
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return err;
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}
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static void ctch_close(struct intel_guc *guc,
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struct intel_guc_ct_channel *ctch)
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{
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GEM_BUG_ON(!ctch_is_open(ctch));
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guc_action_deregister_ct_buffer(guc,
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ctch->owner,
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INTEL_GUC_CT_BUFFER_TYPE_SEND);
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guc_action_deregister_ct_buffer(guc,
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ctch->owner,
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INTEL_GUC_CT_BUFFER_TYPE_RECV);
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ctch_fini(guc, ctch);
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}
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static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
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{
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/* For now it's trivial */
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return ++ctch->next_fence;
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}
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static int ctb_write(struct intel_guc_ct_buffer *ctb,
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const u32 *action,
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u32 len /* in dwords */,
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u32 fence)
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{
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struct guc_ct_buffer_desc *desc = ctb->desc;
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u32 head = desc->head / 4; /* in dwords */
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u32 tail = desc->tail / 4; /* in dwords */
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u32 size = desc->size / 4; /* in dwords */
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u32 used; /* in dwords */
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u32 header;
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u32 *cmds = ctb->cmds;
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unsigned int i;
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GEM_BUG_ON(desc->size % 4);
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GEM_BUG_ON(desc->head % 4);
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GEM_BUG_ON(desc->tail % 4);
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GEM_BUG_ON(tail >= size);
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/*
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* tail == head condition indicates empty. GuC FW does not support
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* using up the entire buffer to get tail == head meaning full.
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*/
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if (tail < head)
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used = (size - head) + tail;
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else
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used = tail - head;
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/* make sure there is a space including extra dw for the fence */
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if (unlikely(used + len + 1 >= size))
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return -ENOSPC;
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/* Write the message. The format is the following:
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* DW0: header (including action code)
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* DW1: fence
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* DW2+: action data
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*/
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header = (len << GUC_CT_MSG_LEN_SHIFT) |
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(GUC_CT_MSG_WRITE_FENCE_TO_DESC) |
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(action[0] << GUC_CT_MSG_ACTION_SHIFT);
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cmds[tail] = header;
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tail = (tail + 1) % size;
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cmds[tail] = fence;
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tail = (tail + 1) % size;
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for (i = 1; i < len; i++) {
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cmds[tail] = action[i];
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tail = (tail + 1) % size;
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}
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/* now update desc tail (back in bytes) */
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desc->tail = tail * 4;
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GEM_BUG_ON(desc->tail > desc->size);
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return 0;
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}
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/* Wait for the response from the GuC.
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* @fence: response fence
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* @status: placeholder for status
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* return: 0 response received (status is valid)
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* -ETIMEDOUT no response within hardcoded timeout
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* -EPROTO no response, ct buffer was in error
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*/
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static int wait_for_response(struct guc_ct_buffer_desc *desc,
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u32 fence,
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u32 *status)
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{
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int err;
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/*
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* Fast commands should complete in less than 10us, so sample quickly
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* up to that length of time, then switch to a slower sleep-wait loop.
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* No GuC command should ever take longer than 10ms.
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*/
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#define done (READ_ONCE(desc->fence) == fence)
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err = wait_for_us(done, 10);
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if (err)
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err = wait_for(done, 10);
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#undef done
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if (unlikely(err)) {
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DRM_ERROR("CT: fence %u failed; reported fence=%u\n",
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fence, desc->fence);
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if (WARN_ON(desc->is_in_error)) {
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/* Something went wrong with the messaging, try to reset
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* the buffer and hope for the best
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*/
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guc_ct_buffer_desc_reset(desc);
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err = -EPROTO;
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}
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}
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*status = desc->status;
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return err;
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}
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static int ctch_send(struct intel_guc *guc,
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struct intel_guc_ct_channel *ctch,
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const u32 *action,
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u32 len,
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u32 *status)
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{
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struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_SEND];
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struct guc_ct_buffer_desc *desc = ctb->desc;
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u32 fence;
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int err;
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GEM_BUG_ON(!ctch_is_open(ctch));
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GEM_BUG_ON(!len);
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GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
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fence = ctch_get_next_fence(ctch);
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err = ctb_write(ctb, action, len, fence);
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if (unlikely(err))
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return err;
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intel_guc_notify(guc);
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err = wait_for_response(desc, fence, status);
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if (unlikely(err))
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return err;
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if (*status != INTEL_GUC_STATUS_SUCCESS)
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return -EIO;
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return 0;
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}
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/*
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* Command Transport (CT) buffer based GuC send function.
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*/
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static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len)
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{
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struct intel_guc_ct_channel *ctch = &guc->ct.host_channel;
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u32 status = ~0; /* undefined */
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int err;
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mutex_lock(&guc->send_mutex);
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err = ctch_send(guc, ctch, action, len, &status);
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if (unlikely(err)) {
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DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
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action[0], err, status);
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}
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mutex_unlock(&guc->send_mutex);
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return err;
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}
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/**
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* Enable buffer based command transport
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* Shall only be called for platforms with HAS_GUC_CT.
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* @guc: the guc
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* return: 0 on success
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* non-zero on failure
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*/
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int intel_guc_enable_ct(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_guc_ct_channel *ctch = &guc->ct.host_channel;
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int err;
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GEM_BUG_ON(!HAS_GUC_CT(dev_priv));
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err = ctch_open(guc, ctch);
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if (unlikely(err))
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return err;
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/* Switch into cmd transport buffer based send() */
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guc->send = intel_guc_send_ct;
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DRM_INFO("CT: %s\n", enableddisabled(true));
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return 0;
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}
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/**
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* Disable buffer based command transport.
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* Shall only be called for platforms with HAS_GUC_CT.
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* @guc: the guc
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*/
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void intel_guc_disable_ct(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_guc_ct_channel *ctch = &guc->ct.host_channel;
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GEM_BUG_ON(!HAS_GUC_CT(dev_priv));
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if (!ctch_is_open(ctch))
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return;
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ctch_close(guc, ctch);
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/* Disable send */
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guc->send = intel_guc_send_nop;
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DRM_INFO("CT: %s\n", enableddisabled(false));
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}
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