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389 lines
11 KiB
389 lines
11 KiB
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eddie Dong <eddie.dong@intel.com>
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* Jike Song <jike.song@intel.com>
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*
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* Contributors:
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* Zhi Wang <zhi.a.wang@intel.com>
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* Min He <min.he@intel.com>
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* Bing Niu <bing.niu@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "gvt.h"
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enum {
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INTEL_GVT_PCI_BAR_GTTMMIO = 0,
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INTEL_GVT_PCI_BAR_APERTURE,
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INTEL_GVT_PCI_BAR_PIO,
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INTEL_GVT_PCI_BAR_MAX,
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};
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/* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one
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* byte) byte by byte in standard pci configuration space. (not the full
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* 256 bytes.)
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*/
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static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = {
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[PCI_COMMAND] = 0xff, 0x07,
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[PCI_STATUS] = 0x00, 0xf9, /* the only one RW1C byte */
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[PCI_CACHE_LINE_SIZE] = 0xff,
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[PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff,
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[PCI_ROM_ADDRESS] = 0x01, 0xf8, 0xff, 0xff,
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[PCI_INTERRUPT_LINE] = 0xff,
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};
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/**
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* vgpu_pci_cfg_mem_write - write virtual cfg space memory
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*
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* Use this function to write virtual cfg space memory.
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* For standard cfg space, only RW bits can be changed,
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* and we emulates the RW1C behavior of PCI_STATUS register.
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*/
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static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,
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u8 *src, unsigned int bytes)
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{
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u8 *cfg_base = vgpu_cfg_space(vgpu);
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u8 mask, new, old;
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int i = 0;
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for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) {
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mask = pci_cfg_space_rw_bmp[off + i];
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old = cfg_base[off + i];
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new = src[i] & mask;
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/**
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* The PCI_STATUS high byte has RW1C bits, here
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* emulates clear by writing 1 for these bits.
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* Writing a 0b to RW1C bits has no effect.
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*/
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if (off + i == PCI_STATUS + 1)
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new = (~new & old) & mask;
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cfg_base[off + i] = (old & ~mask) | new;
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}
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/* For other configuration space directly copy as it is. */
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if (i < bytes)
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memcpy(cfg_base + off + i, src + i, bytes - i);
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}
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/**
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* intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
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*
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* Returns:
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* Zero on success, negative error code if failed.
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*/
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int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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if (WARN_ON(bytes > 4))
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return -EINVAL;
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if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
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return -EINVAL;
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memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
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return 0;
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}
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static int map_aperture(struct intel_vgpu *vgpu, bool map)
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{
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u64 first_gfn, first_mfn;
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u64 val;
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int ret;
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if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
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return 0;
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val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];
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if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
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val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
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else
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val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
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first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT;
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first_mfn = vgpu_aperture_pa_base(vgpu) >> PAGE_SHIFT;
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ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn,
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first_mfn,
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vgpu_aperture_sz(vgpu) >>
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PAGE_SHIFT, map);
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if (ret)
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return ret;
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vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
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return 0;
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}
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static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap)
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{
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u64 start, end;
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u64 val;
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int ret;
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if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)
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return 0;
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val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0];
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if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
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start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
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else
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start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
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start &= ~GENMASK(3, 0);
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end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1;
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ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap);
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if (ret)
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return ret;
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vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;
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return 0;
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}
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static int emulate_pci_command_write(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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u8 old = vgpu_cfg_space(vgpu)[offset];
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u8 new = *(u8 *)p_data;
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u8 changed = old ^ new;
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int ret;
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vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
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if (!(changed & PCI_COMMAND_MEMORY))
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return 0;
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if (old & PCI_COMMAND_MEMORY) {
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ret = trap_gttmmio(vgpu, false);
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if (ret)
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return ret;
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ret = map_aperture(vgpu, false);
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if (ret)
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return ret;
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} else {
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ret = trap_gttmmio(vgpu, true);
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if (ret)
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return ret;
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ret = map_aperture(vgpu, true);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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u32 new = *(u32 *)(p_data);
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bool lo = IS_ALIGNED(offset, 8);
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u64 size;
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int ret = 0;
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bool mmio_enabled =
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vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
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struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;
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/*
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* Power-up software can determine how much address
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* space the device requires by writing a value of
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* all 1's to the register and then reading the value
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* back. The device will return 0's in all don't-care
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* address bits.
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*/
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if (new == 0xffffffff) {
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switch (offset) {
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1:
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size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1);
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intel_vgpu_write_pci_bar(vgpu, offset,
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size >> (lo ? 0 : 32), lo);
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/*
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* Untrap the BAR, since guest hasn't configured a
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* valid GPA
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*/
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ret = trap_gttmmio(vgpu, false);
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break;
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case PCI_BASE_ADDRESS_2:
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case PCI_BASE_ADDRESS_3:
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size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1);
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intel_vgpu_write_pci_bar(vgpu, offset,
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size >> (lo ? 0 : 32), lo);
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ret = map_aperture(vgpu, false);
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break;
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default:
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/* Unimplemented BARs */
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intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false);
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}
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} else {
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switch (offset) {
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1:
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/*
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* Untrap the old BAR first, since guest has
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* re-configured the BAR
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*/
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trap_gttmmio(vgpu, false);
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intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
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ret = trap_gttmmio(vgpu, mmio_enabled);
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break;
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case PCI_BASE_ADDRESS_2:
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case PCI_BASE_ADDRESS_3:
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map_aperture(vgpu, false);
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intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
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ret = map_aperture(vgpu, mmio_enabled);
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break;
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default:
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intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
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}
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}
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return ret;
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}
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/**
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* intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
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*
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* Returns:
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* Zero on success, negative error code if failed.
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*/
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int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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int ret;
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if (WARN_ON(bytes > 4))
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return -EINVAL;
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if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
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return -EINVAL;
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/* First check if it's PCI_COMMAND */
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if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {
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if (WARN_ON(bytes > 2))
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return -EINVAL;
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return emulate_pci_command_write(vgpu, offset, p_data, bytes);
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}
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switch (rounddown(offset, 4)) {
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case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
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if (WARN_ON(!IS_ALIGNED(offset, 4)))
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return -EINVAL;
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return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
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case INTEL_GVT_PCI_SWSCI:
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if (WARN_ON(!IS_ALIGNED(offset, 4)))
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return -EINVAL;
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ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);
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if (ret)
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return ret;
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break;
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case INTEL_GVT_PCI_OPREGION:
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if (WARN_ON(!IS_ALIGNED(offset, 4)))
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return -EINVAL;
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ret = intel_vgpu_init_opregion(vgpu, *(u32 *)p_data);
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if (ret)
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return ret;
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vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
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break;
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default:
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vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
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break;
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}
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return 0;
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}
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/**
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* intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU
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*
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* @vgpu: a vGPU
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* @primary: is the vGPU presented as primary
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*
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*/
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void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
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bool primary)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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const struct intel_gvt_device_info *info = &gvt->device_info;
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u16 *gmch_ctl;
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memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
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info->cfg_space_size);
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if (!primary) {
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vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =
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INTEL_GVT_PCI_CLASS_VGA_OTHER;
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vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =
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INTEL_GVT_PCI_CLASS_VGA_OTHER;
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}
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/* Show guest that there isn't any stolen memory.*/
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gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);
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*gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT);
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intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2,
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gvt_aperture_pa_base(gvt), true);
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vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO
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| PCI_COMMAND_MEMORY
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| PCI_COMMAND_MASTER);
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/*
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* Clear the bar upper 32bit and let guest to assign the new value
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*/
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memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
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memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
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memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
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memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
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vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
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pci_resource_len(gvt->dev_priv->drm.pdev, 0);
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vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
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pci_resource_len(gvt->dev_priv->drm.pdev, 2);
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}
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/**
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* intel_vgpu_reset_cfg_space - reset vGPU configuration space
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*
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* @vgpu: a vGPU
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*
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*/
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void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu)
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{
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u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND];
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bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] !=
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INTEL_GVT_PCI_CLASS_VGA_OTHER;
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if (cmd & PCI_COMMAND_MEMORY) {
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trap_gttmmio(vgpu, false);
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map_aperture(vgpu, false);
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}
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/**
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* Currently we only do such reset when vGPU is not
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* owned by any VM, so we simply restore entire cfg
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* space to default value.
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*/
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intel_vgpu_init_cfg_space(vgpu, primary);
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}
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