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150 lines
3.3 KiB
150 lines
3.3 KiB
/*
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* Clock tree for CSR SiRFprimaII
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*
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* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
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* company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include "prima2.h"
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#include "clk-common.c"
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static struct clk_dmn clk_mmc01 = {
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.regofs = SIRFSOC_CLKC_MMC_CFG,
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.enable_bit = 59,
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.hw = {
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.init = &clk_mmc01_init,
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},
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};
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static struct clk_dmn clk_mmc23 = {
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.regofs = SIRFSOC_CLKC_MMC_CFG,
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.enable_bit = 60,
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.hw = {
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.init = &clk_mmc23_init,
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},
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};
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static struct clk_dmn clk_mmc45 = {
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.regofs = SIRFSOC_CLKC_MMC_CFG,
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.enable_bit = 61,
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.hw = {
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.init = &clk_mmc45_init,
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},
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};
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static struct clk_init_data clk_nand_init = {
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.name = "nand",
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.ops = &ios_ops,
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.parent_names = std_clk_io_parents,
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.num_parents = ARRAY_SIZE(std_clk_io_parents),
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};
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static struct clk_std clk_nand = {
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.enable_bit = 34,
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.hw = {
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.init = &clk_nand_init,
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},
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};
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enum prima2_clk_index {
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/* 0 1 2 3 4 5 6 7 8 9 */
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rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
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mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
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spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
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usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
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usb0, usb1, cphif, maxclk,
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};
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static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = {
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NULL, /* dummy */
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NULL,
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&clk_pll1.hw,
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&clk_pll2.hw,
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&clk_pll3.hw,
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&clk_mem.hw,
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&clk_sys.hw,
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&clk_security.hw,
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&clk_dsp.hw,
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&clk_gps.hw,
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&clk_mf.hw,
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&clk_io.hw,
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&clk_cpu.hw,
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&clk_uart0.hw,
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&clk_uart1.hw,
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&clk_uart2.hw,
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&clk_tsc.hw,
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&clk_i2c0.hw,
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&clk_i2c1.hw,
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&clk_spi0.hw,
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&clk_spi1.hw,
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&clk_pwmc.hw,
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&clk_efuse.hw,
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&clk_pulse.hw,
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&clk_dmac0.hw,
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&clk_dmac1.hw,
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&clk_nand.hw,
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&clk_audio.hw,
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&clk_usp0.hw,
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&clk_usp1.hw,
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&clk_usp2.hw,
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&clk_vip.hw,
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&clk_gfx.hw,
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&clk_mm.hw,
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&clk_lcd.hw,
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&clk_vpp.hw,
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&clk_mmc01.hw,
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&clk_mmc23.hw,
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&clk_mmc45.hw,
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&usb_pll_clk_hw,
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&clk_usb0.hw,
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&clk_usb1.hw,
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&clk_cphif.hw,
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};
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static struct clk *prima2_clks[maxclk];
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static void __init prima2_clk_init(struct device_node *np)
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{
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struct device_node *rscnp;
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int i;
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rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
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sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
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if (!sirfsoc_rsc_vbase)
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panic("unable to map rsc registers\n");
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of_node_put(rscnp);
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sirfsoc_clk_vbase = of_iomap(np, 0);
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if (!sirfsoc_clk_vbase)
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panic("unable to map clkc registers\n");
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/* These are always available (RTC and 26MHz OSC)*/
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prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
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prima2_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0,
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26000000);
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for (i = pll1; i < maxclk; i++) {
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prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
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BUG_ON(!prima2_clks[i]);
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}
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clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
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clk_register_clkdev(prima2_clks[io], NULL, "io");
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clk_register_clkdev(prima2_clks[mem], NULL, "mem");
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clk_register_clkdev(prima2_clks[mem], NULL, "osc");
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clk_data.clks = prima2_clks;
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clk_data.clk_num = maxclk;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init);
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