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397 lines
10 KiB
397 lines
10 KiB
/*
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* R-Car Gen3 Clock Pulse Generator
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*
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* Copyright (C) 2015-2016 Glider bvba
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*
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* Based on clk-rcar-gen3.c
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/bug.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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#define CPG_PLL0CR 0x00d8
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#define CPG_PLL2CR 0x002c
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#define CPG_PLL4CR 0x01f4
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/*
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* SDn Clock
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*/
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#define CPG_SD_STP_HCK BIT(9)
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#define CPG_SD_STP_CK BIT(8)
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#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
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#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
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#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
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{ \
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.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
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((stp_ck) ? CPG_SD_STP_CK : 0) | \
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((sd_srcfc) << 2) | \
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((sd_fc) << 0), \
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.div = (sd_div), \
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}
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struct sd_div_table {
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u32 val;
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unsigned int div;
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};
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struct sd_clock {
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struct clk_hw hw;
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void __iomem *reg;
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const struct sd_div_table *div_table;
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unsigned int div_num;
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unsigned int div_min;
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unsigned int div_max;
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unsigned int cur_div_idx;
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};
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/* SDn divider
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* sd_srcfc sd_fc div
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* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
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*-------------------------------------------------------------------
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* 0 0 0 (1) 1 (4) 4
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* 0 0 1 (2) 1 (4) 8
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* 1 0 2 (4) 1 (4) 16
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* 1 0 3 (8) 1 (4) 32
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* 1 0 4 (16) 1 (4) 64
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* 0 0 0 (1) 0 (2) 2
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* 0 0 1 (2) 0 (2) 4
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* 1 0 2 (4) 0 (2) 8
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* 1 0 3 (8) 0 (2) 16
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* 1 0 4 (16) 0 (2) 32
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*/
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static const struct sd_div_table cpg_sd_div_table[] = {
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/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
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};
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#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
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static int cpg_sd_clock_enable(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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u32 val = readl(clock->reg);
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val &= ~(CPG_SD_STP_MASK);
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val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
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writel(val, clock->reg);
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return 0;
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}
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static void cpg_sd_clock_disable(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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writel(readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
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}
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static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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return !(readl(clock->reg) & CPG_SD_STP_MASK);
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}
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static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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return DIV_ROUND_CLOSEST(parent_rate,
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clock->div_table[clock->cur_div_idx].div);
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}
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static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
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unsigned long rate,
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unsigned long parent_rate)
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{
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unsigned int div;
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if (!rate)
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rate = 1;
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
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}
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static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
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return DIV_ROUND_CLOSEST(*parent_rate, div);
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}
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static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
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u32 val;
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unsigned int i;
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for (i = 0; i < clock->div_num; i++)
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if (div == clock->div_table[i].div)
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break;
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if (i >= clock->div_num)
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return -EINVAL;
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clock->cur_div_idx = i;
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val = readl(clock->reg);
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val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
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val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
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writel(val, clock->reg);
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return 0;
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}
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static const struct clk_ops cpg_sd_clock_ops = {
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.enable = cpg_sd_clock_enable,
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.disable = cpg_sd_clock_disable,
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.is_enabled = cpg_sd_clock_is_enabled,
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.recalc_rate = cpg_sd_clock_recalc_rate,
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.round_rate = cpg_sd_clock_round_rate,
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.set_rate = cpg_sd_clock_set_rate,
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};
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static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
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void __iomem *base,
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const char *parent_name)
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{
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struct clk_init_data init;
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struct sd_clock *clock;
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struct clk *clk;
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unsigned int i;
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u32 sd_fc;
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clock = kzalloc(sizeof(*clock), GFP_KERNEL);
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if (!clock)
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return ERR_PTR(-ENOMEM);
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init.name = core->name;
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init.ops = &cpg_sd_clock_ops;
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init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clock->reg = base + core->offset;
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clock->hw.init = &init;
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clock->div_table = cpg_sd_div_table;
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clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
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sd_fc = readl(clock->reg) & CPG_SD_FC_MASK;
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for (i = 0; i < clock->div_num; i++)
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if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
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break;
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if (WARN_ON(i >= clock->div_num)) {
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kfree(clock);
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return ERR_PTR(-EINVAL);
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}
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clock->cur_div_idx = i;
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clock->div_max = clock->div_table[0].div;
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clock->div_min = clock->div_max;
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for (i = 1; i < clock->div_num; i++) {
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clock->div_max = max(clock->div_max, clock->div_table[i].div);
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clock->div_min = min(clock->div_min, clock->div_table[i].div);
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}
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clk = clk_register(NULL, &clock->hw);
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if (IS_ERR(clk))
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kfree(clock);
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return clk;
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}
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static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
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static unsigned int cpg_clk_extalr __initdata;
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static u32 cpg_mode __initdata;
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static u32 cpg_quirks __initdata;
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#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
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#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
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static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
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{
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.soc_id = "r8a7795", .revision = "ES1.0",
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.data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
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},
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{
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.soc_id = "r8a7795", .revision = "ES1.*",
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.data = (void *)RCKCR_CKSEL,
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},
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{
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.soc_id = "r8a7796", .revision = "ES1.0",
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.data = (void *)RCKCR_CKSEL,
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},
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{ /* sentinel */ }
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};
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struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base)
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{
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const struct clk *parent;
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unsigned int mult = 1;
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unsigned int div = 1;
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u32 value;
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parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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switch (core->type) {
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case CLK_TYPE_GEN3_MAIN:
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div = cpg_pll_config->extal_div;
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break;
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case CLK_TYPE_GEN3_PLL0:
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/*
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* PLL0 is a configurable multiplier clock. Register it as a
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* fixed factor clock for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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value = readl(base + CPG_PLL0CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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if (cpg_quirks & PLL_ERRATA)
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mult *= 2;
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break;
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case CLK_TYPE_GEN3_PLL1:
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mult = cpg_pll_config->pll1_mult;
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div = cpg_pll_config->pll1_div;
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break;
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case CLK_TYPE_GEN3_PLL2:
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/*
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* PLL2 is a configurable multiplier clock. Register it as a
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* fixed factor clock for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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value = readl(base + CPG_PLL2CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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if (cpg_quirks & PLL_ERRATA)
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mult *= 2;
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break;
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case CLK_TYPE_GEN3_PLL3:
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mult = cpg_pll_config->pll3_mult;
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div = cpg_pll_config->pll3_div;
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break;
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case CLK_TYPE_GEN3_PLL4:
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/*
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* PLL4 is a configurable multiplier clock. Register it as a
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* fixed factor clock for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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value = readl(base + CPG_PLL4CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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if (cpg_quirks & PLL_ERRATA)
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mult *= 2;
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break;
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case CLK_TYPE_GEN3_SD:
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return cpg_sd_clk_register(core, base, __clk_get_name(parent));
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case CLK_TYPE_GEN3_R:
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if (cpg_quirks & RCKCR_CKSEL) {
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/*
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* RINT is default.
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* Only if EXTALR is populated, we switch to it.
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*/
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value = readl(base + CPG_RCKCR) & 0x3f;
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if (clk_get_rate(clks[cpg_clk_extalr])) {
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parent = clks[cpg_clk_extalr];
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value |= BIT(15);
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}
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writel(value, base + CPG_RCKCR);
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break;
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}
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/* Select parent clock of RCLK by MD28 */
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if (cpg_mode & BIT(28))
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parent = clks[cpg_clk_extalr];
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break;
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case CLK_TYPE_GEN3_PE:
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/*
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* Peripheral clock with a fixed divider, selectable between
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* clean and spread spectrum parents using MD12
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*/
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if (cpg_mode & BIT(12)) {
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/* Clean */
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div = core->div & 0xffff;
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} else {
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/* SCCG */
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parent = clks[core->parent >> 16];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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div = core->div >> 16;
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}
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mult = 1;
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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return clk_register_fixed_factor(NULL, core->name,
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__clk_get_name(parent), 0, mult, div);
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}
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int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
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unsigned int clk_extalr, u32 mode)
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{
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const struct soc_device_attribute *attr;
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cpg_pll_config = config;
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cpg_clk_extalr = clk_extalr;
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cpg_mode = mode;
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attr = soc_device_match(cpg_quirks_match);
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if (attr)
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cpg_quirks = (uintptr_t)attr->data;
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pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
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return 0;
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}
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