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310 lines
8.4 KiB
310 lines
8.4 KiB
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/*
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* Display Port PLL driver block diagram for branch clocks
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*
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* +------------------------------+
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* | DP_VCO_CLK |
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* | |
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* | +-------------------+ |
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* | | (DP PLL/VCO) | |
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* | +---------+---------+ |
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* | v |
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* | +----------+-----------+ |
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* | | hsclk_divsel_clk_src | |
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* | +----------+-----------+ |
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* +------------------------------+
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* |
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* +------------<---------v------------>----------+
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* | |
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* +-----v------------+ |
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* | dp_link_clk_src | |
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* | divsel_ten | |
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* +---------+--------+ |
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* | |
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* | |
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* v v
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* Input to DISPCC block |
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* for link clk, crypto clk |
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* and interface clock |
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* |
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* |
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* +--------<------------+-----------------+---<---+
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* | | |
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* +-------v------+ +--------v-----+ +--------v------+
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* | vco_divided | | vco_divided | | vco_divided |
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* | _clk_src | | _clk_src | | _clk_src |
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* | | | | | |
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* |divsel_six | | divsel_two | | divsel_four |
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* +-------+------+ +-----+--------+ +--------+------+
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* | | |
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* v------->----------v-------------<------v
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* |
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* +----------+---------+
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* | vco_divided_clk |
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* | _src_mux |
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* +---------+----------+
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* |
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* v
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* Input to DISPCC block
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* for DP pixel clock
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*
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
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#include "mdss-pll.h"
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#include "mdss-dp-pll.h"
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#include "mdss-dp-pll-10nm.h"
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static struct dp_pll_db dp_pdb;
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static struct clk_ops mux_clk_ops;
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static struct regmap_config dp_pll_10nm_cfg = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x910,
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};
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static struct regmap_bus dp_pixel_mux_regmap_ops = {
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.reg_write = dp_mux_set_parent_10nm,
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.reg_read = dp_mux_get_parent_10nm,
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};
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/* Op structures */
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static const struct clk_ops dp_10nm_vco_clk_ops = {
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.recalc_rate = dp_vco_recalc_rate_10nm,
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.set_rate = dp_vco_set_rate_10nm,
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.round_rate = dp_vco_round_rate_10nm,
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.prepare = dp_vco_prepare_10nm,
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.unprepare = dp_vco_unprepare_10nm,
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};
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static struct dp_pll_vco_clk dp_vco_clk = {
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.min_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000,
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.max_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000,
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.hw.init = &(struct clk_init_data){
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.name = "dp_vco_clk",
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.parent_names = (const char *[]){ "xo_board" },
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.num_parents = 1,
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.ops = &dp_10nm_vco_clk_ops,
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},
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};
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static struct clk_fixed_factor dp_phy_pll_link_clk = {
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.div = 10,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dp_phy_pll_link_clk",
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.parent_names =
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(const char *[]){ "dp_vco_clk" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dp_vco_divsel_two_clk_src = {
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.div = 2,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dp_vco_divsel_two_clk_src",
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.parent_names =
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(const char *[]){ "dp_vco_clk" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dp_vco_divsel_four_clk_src = {
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.div = 4,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dp_vco_divsel_four_clk_src",
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.parent_names =
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(const char *[]){ "dp_vco_clk" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dp_vco_divsel_six_clk_src = {
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.div = 6,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dp_vco_divsel_six_clk_src",
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.parent_names =
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(const char *[]){ "dp_vco_clk" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static int clk_mux_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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int ret = 0;
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ret = __clk_mux_determine_rate_closest(hw, req);
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if (ret)
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return ret;
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/* Set the new parent of mux if there is a new valid parent */
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if (hw->clk && req->best_parent_hw->clk)
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clk_set_parent(hw->clk, req->best_parent_hw->clk);
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return 0;
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}
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static unsigned long mux_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk *div_clk = NULL, *vco_clk = NULL;
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struct dp_pll_vco_clk *vco = NULL;
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div_clk = clk_get_parent(hw->clk);
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if (!div_clk)
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return 0;
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vco_clk = clk_get_parent(div_clk);
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if (!vco_clk)
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return 0;
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vco = to_dp_vco_hw(__clk_get_hw(vco_clk));
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if (!vco)
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return 0;
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if (vco->rate == DP_VCO_HSCLK_RATE_8100MHZDIV1000)
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return (vco->rate / 6);
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else if (vco->rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000)
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return (vco->rate / 4);
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else
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return (vco->rate / 2);
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}
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static struct clk_regmap_mux dp_phy_pll_vco_div_clk = {
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.reg = 0x64,
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.shift = 0,
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.width = 2,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dp_phy_pll_vco_div_clk",
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.parent_names =
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(const char *[]){"dp_vco_divsel_two_clk_src",
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"dp_vco_divsel_four_clk_src",
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"dp_vco_divsel_six_clk_src"},
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.num_parents = 3,
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.ops = &mux_clk_ops,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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},
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},
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};
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static struct clk_hw *mdss_dp_pllcc_10nm[] = {
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[DP_VCO_CLK] = &dp_vco_clk.hw,
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[DP_LINK_CLK_DIVSEL_TEN] = &dp_phy_pll_link_clk.hw,
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[DP_VCO_DIVIDED_TWO_CLK_SRC] = &dp_vco_divsel_two_clk_src.hw,
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[DP_VCO_DIVIDED_FOUR_CLK_SRC] = &dp_vco_divsel_four_clk_src.hw,
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[DP_VCO_DIVIDED_SIX_CLK_SRC] = &dp_vco_divsel_six_clk_src.hw,
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[DP_VCO_DIVIDED_CLK_SRC_MUX] = &dp_phy_pll_vco_div_clk.clkr.hw,
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};
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int dp_pll_clock_register_10nm(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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int rc = -ENOTSUPP, i = 0;
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struct clk_onecell_data *clk_data;
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struct clk *clk;
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struct regmap *regmap;
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int num_clks = ARRAY_SIZE(mdss_dp_pllcc_10nm);
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if (!pdev || !pdev->dev.of_node) {
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pr_err("Invalid input parameters\n");
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return -EINVAL;
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}
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if (!pll_res || !pll_res->pll_base || !pll_res->phy_base ||
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!pll_res->ln_tx0_base || !pll_res->ln_tx1_base) {
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pr_err("%s: Invalid input parameters\n", __func__);
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return -EINVAL;
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}
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clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->clks = devm_kzalloc(&pdev->dev, (num_clks *
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sizeof(struct clk *)), GFP_KERNEL);
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if (!clk_data->clks) {
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devm_kfree(&pdev->dev, clk_data);
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return -ENOMEM;
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}
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clk_data->clk_num = num_clks;
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pll_res->priv = &dp_pdb;
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dp_pdb.pll = pll_res;
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/* Set client data for vco, mux and div clocks */
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regmap = devm_regmap_init(&pdev->dev, &dp_pixel_mux_regmap_ops,
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pll_res, &dp_pll_10nm_cfg);
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dp_phy_pll_vco_div_clk.clkr.regmap = regmap;
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mux_clk_ops = clk_regmap_mux_closest_ops;
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mux_clk_ops.determine_rate = clk_mux_determine_rate;
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mux_clk_ops.recalc_rate = mux_recalc_rate;
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dp_vco_clk.priv = pll_res;
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for (i = DP_VCO_CLK; i <= DP_VCO_DIVIDED_CLK_SRC_MUX; i++) {
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pr_debug("reg clk: %d index: %d\n", i, pll_res->index);
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clk = devm_clk_register(&pdev->dev,
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mdss_dp_pllcc_10nm[i]);
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if (IS_ERR(clk)) {
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pr_err("clk registration failed for DP: %d\n",
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pll_res->index);
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rc = -EINVAL;
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goto clk_reg_fail;
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}
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clk_data->clks[i] = clk;
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}
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rc = of_clk_add_provider(pdev->dev.of_node,
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of_clk_src_onecell_get, clk_data);
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if (rc) {
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pr_err("%s: Clock register failed rc=%d\n", __func__, rc);
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rc = -EPROBE_DEFER;
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} else {
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pr_debug("%s SUCCESS\n", __func__);
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}
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return 0;
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clk_reg_fail:
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devm_kfree(&pdev->dev, clk_data->clks);
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devm_kfree(&pdev->dev, clk_data);
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return rc;
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}
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