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568 lines
14 KiB
568 lines
14 KiB
/*
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* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/qcom,gpu-sdm660.h>
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#include "clk-alpha-pll.h"
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "vdd-level-660.h"
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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#define F_GFX(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) }
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static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner);
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static DEFINE_VDD_REGS_INIT(vdd_gfx, 1);
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enum {
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P_XO,
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P_CORE_BI_PLL_TEST_SE,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_PLL0_PLL_OUT_MAIN,
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P_GPU_PLL1_PLL_OUT_MAIN,
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};
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static const struct parent_map gpucc_parent_map_0[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gpucc_parent_names_0[] = {
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"cxo_a",
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"gcc_gpu_gpll0_clk",
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"gcc_gpu_gpll0_div_clk",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gpucc_parent_map_1[] = {
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{ P_XO, 0 },
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{ P_GPU_PLL0_PLL_OUT_MAIN, 1 },
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{ P_GPU_PLL1_PLL_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gpucc_parent_names_1[] = {
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"xo",
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"gpu_pll0_pll_out_main",
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"gpu_pll1_pll_out_main",
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"gcc_gpu_gpll0_clk",
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"core_bi_pll_test_se",
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};
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static struct pll_vco gpu_vco[] = {
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{ 1000000000, 2000000000, 0 },
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{ 500000000, 1000000000, 2 },
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{ 250000000, 500000000, 3 },
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};
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/* 800MHz configuration */
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static const struct alpha_pll_config gpu_pll0_config = {
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.l = 0x29,
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.config_ctl_val = 0x4001055b,
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.alpha = 0xaaaaab00,
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.alpha_u = 0xaa,
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.alpha_en_mask = BIT(24),
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.vco_val = 0x2 << 20,
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.vco_mask = 0x3 << 20,
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.main_output_mask = 0x1,
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};
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static struct pll_vco_data pll_data[] = {
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/* Frequency post-div */
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{ 640000000, 0x1 },
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};
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static struct clk_alpha_pll gpu_pll0_pll_out_main = {
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.offset = 0x0,
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.vco_table = gpu_vco,
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.num_vco = ARRAY_SIZE(gpu_vco),
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.vco_data = pll_data,
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.num_vco_data = ARRAY_SIZE(pll_data),
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_pll0_pll_out_main",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000),
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},
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},
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};
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static struct clk_alpha_pll gpu_pll1_pll_out_main = {
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.offset = 0x40,
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.vco_table = gpu_vco,
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.num_vco = ARRAY_SIZE(gpu_vco),
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.vco_data = pll_data,
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.num_vco_data = ARRAY_SIZE(pll_data),
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_pll1_pll_out_main",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000),
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},
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},
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};
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/* GFX clock init data */
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static struct clk_init_data gpu_clks_init[] = {
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[0] = {
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.name = "gfx3d_clk_src",
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.parent_names = gpucc_parent_names_1,
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.num_parents = 3,
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.ops = &clk_gfx3d_src_ops,
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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},
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[1] = {
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.name = "gpucc_gfx3d_clk",
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.parent_names = (const char *[]){
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"gfx3d_clk_src",
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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.flags = CLK_SET_RATE_PARENT,
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.vdd_class = &vdd_gfx,
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},
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};
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/*
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* Frequencies and PLL configuration
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* The PLL source would be to ping-pong between GPU-PLL0
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* and GPU-PLL1.
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* ====================================================
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* | F | PLL SRC Freq | PLL postdiv | RCG Div |
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* ====================================================
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* | 160000000 | 640000000 | 2 | 2 |
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* | 266000000 | 532000000 | 1 | 2 |
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* | 370000000 | 740000000 | 1 | 2 |
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* | 465000000 | 930000000 | 1 | 2 |
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* | 588000000 | 1176000000 | 1 | 2 |
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* | 647000000 | 1294000000 | 1 | 2 |
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* | 700000000 | 1400000000 | 1 | 2 |
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* | 750000000 | 1500000000 | 1 | 2 |
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* ====================================================
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*/
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static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
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F_GFX( 19200000, 0, 1, 0, 0, 0),
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F_GFX(160000000, 0, 2, 0, 0, 640000000),
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F_GFX(266000000, 0, 2, 0, 0, 532000000),
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F_GFX(370000000, 0, 2, 0, 0, 740000000),
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F_GFX(430000000, 0, 2, 0, 0, 860000000),
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F_GFX(465000000, 0, 2, 0, 0, 930000000),
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F_GFX(585000000, 0, 2, 0, 0, 1170000000),
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F_GFX(588000000, 0, 2, 0, 0, 1176000000),
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F_GFX(647000000, 0, 2, 0, 0, 1294000000),
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F_GFX(700000000, 0, 2, 0, 0, 1400000000),
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F_GFX(750000000, 0, 2, 0, 0, 1500000000),
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{ }
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};
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static const struct freq_tbl ftbl_gfx3d_clk_src_630[] = {
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F_GFX( 19200000, 0, 1, 0, 0, 0),
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F_GFX(160000000, 0, 2, 0, 0, 640000000),
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F_GFX(240000000, 0, 2, 0, 0, 480000000),
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F_GFX(370000000, 0, 2, 0, 0, 740000000),
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F_GFX(465000000, 0, 2, 0, 0, 930000000),
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F_GFX(588000000, 0, 2, 0, 0, 1176000000),
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F_GFX(647000000, 0, 2, 0, 0, 1294000000),
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F_GFX(700000000, 0, 2, 0, 0, 1400000000),
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F_GFX(775000000, 0, 2, 0, 0, 1550000000),
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{ }
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};
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static struct clk_rcg2 gfx3d_clk_src = {
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.cmd_rcgr = 0x1070,
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.mnd_width = 0,
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.hid_width = 5,
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.freq_tbl = ftbl_gfx3d_clk_src,
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.parent_map = gpucc_parent_map_1,
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.flags = FORCE_ENABLE_RCG,
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.enable_safe_config = true,
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.clkr.hw.init = &gpu_clks_init[0],
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};
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static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 rbbmtimer_clk_src = {
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.cmd_rcgr = 0x10b0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpucc_parent_map_0,
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.freq_tbl = ftbl_rbbmtimer_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "rbbmtimer_clk_src",
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.parent_names = gpucc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_ops,
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VDD_DIG_FMAX_MAP1(MIN, 19200000),
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},
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};
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static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
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{ }
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};
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static struct clk_rcg2 rbcpr_clk_src = {
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.cmd_rcgr = 0x1030,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpucc_parent_map_0,
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.freq_tbl = ftbl_rbcpr_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "rbcpr_clk_src",
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.parent_names = gpucc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch gpucc_cxo_clk = {
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.halt_reg = 0x1020,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1020,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cxo_clk",
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.parent_names = (const char *[]) {
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"cxo_a",
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_gfx3d_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &gpu_clks_init[1],
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},
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};
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static struct clk_branch gpucc_rbbmtimer_clk = {
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.halt_reg = 0x10d0,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x10d0,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_rbbmtimer_clk",
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.parent_names = (const char *[]){
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"rbbmtimer_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_rbcpr_clk = {
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.halt_reg = 0x1054,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1054,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_rbcpr_clk",
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.parent_names = (const char *[]){
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"rbcpr_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *gpucc_660_clocks[] = {
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[GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr,
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[GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr,
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[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
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[GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr,
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[GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr,
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[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
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[GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
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};
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static const struct regmap_config gpucc_660_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x9034,
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.fast_io = true,
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};
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static const struct qcom_cc_desc gpucc_660_desc = {
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.config = &gpucc_660_regmap_config,
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.clks = gpucc_660_clocks,
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.num_clks = ARRAY_SIZE(gpucc_660_clocks),
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};
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static const struct of_device_id gpucc_660_match_table[] = {
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{ .compatible = "qcom,gpucc-sdm660" },
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{ .compatible = "qcom,gpucc-sdm630" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpucc_660_match_table);
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static int of_get_fmax_vdd_class(struct platform_device *pdev,
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struct clk_hw *hw, char *prop_name, u32 index)
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{
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struct device_node *of = pdev->dev.of_node;
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int prop_len, i, j;
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struct clk_vdd_class *vdd = hw->init->vdd_class;
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int num = vdd->num_regulators + 1;
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u32 *array;
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if (!of_find_property(of, prop_name, &prop_len)) {
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dev_err(&pdev->dev, "missing %s\n", prop_name);
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return -EINVAL;
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}
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prop_len /= sizeof(u32);
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if (prop_len % num) {
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dev_err(&pdev->dev, "bad length %d\n", prop_len);
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return -EINVAL;
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}
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prop_len /= num;
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vdd->level_votes = devm_kzalloc(&pdev->dev, prop_len * sizeof(int),
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GFP_KERNEL);
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if (!vdd->level_votes)
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return -ENOMEM;
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vdd->vdd_uv = devm_kzalloc(&pdev->dev,
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prop_len * sizeof(int) * (num - 1), GFP_KERNEL);
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if (!vdd->vdd_uv)
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return -ENOMEM;
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gpu_clks_init[index].rate_max = devm_kzalloc(&pdev->dev, prop_len *
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sizeof(unsigned long), GFP_KERNEL);
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if (!gpu_clks_init[index].rate_max)
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return -ENOMEM;
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array = devm_kzalloc(&pdev->dev, prop_len * sizeof(u32) * num,
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GFP_KERNEL);
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if (!array)
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return -ENOMEM;
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of_property_read_u32_array(of, prop_name, array, prop_len * num);
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for (i = 0; i < prop_len; i++) {
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gpu_clks_init[index].rate_max[i] = array[num * i];
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for (j = 1; j < num; j++) {
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vdd->vdd_uv[(num - 1) * i + (j - 1)] =
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array[num * i + j];
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}
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}
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devm_kfree(&pdev->dev, array);
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vdd->num_levels = prop_len;
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vdd->cur_level = prop_len;
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gpu_clks_init[index].num_rate_max = prop_len;
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return 0;
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}
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static int gpucc_660_probe(struct platform_device *pdev)
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{
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int ret = 0;
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struct regmap *regmap;
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struct resource *res;
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void __iomem *base;
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bool is_630 = 0;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res == NULL) {
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dev_err(&pdev->dev, "Failed to get resources\n");
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return -EINVAL;
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}
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base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(&pdev->dev, base, gpucc_660_desc.config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* CX Regulator for RBBMTimer clock */
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vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_gfx");
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if (IS_ERR(vdd_dig.regulator[0])) {
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if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER))
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dev_err(&pdev->dev,
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"Unable to get vdd_dig regulator\n");
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return PTR_ERR(vdd_dig.regulator[0]);
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}
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/* Mx Regulator for GPU-PLLs */
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vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_gfx");
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if (IS_ERR(vdd_mx.regulator[0])) {
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if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER))
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dev_err(&pdev->dev,
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"Unable to get vdd_mx regulator\n");
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return PTR_ERR(vdd_mx.regulator[0]);
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}
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/* GFX Rail Regulator for GFX3D clock */
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vdd_gfx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gfx");
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if (IS_ERR(vdd_gfx.regulator[0])) {
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if (!(PTR_ERR(vdd_gfx.regulator[0]) == -EPROBE_DEFER))
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dev_err(&pdev->dev,
|
|
"Unable to get vdd_gfx regulator\n");
|
|
return PTR_ERR(vdd_gfx.regulator[0]);
|
|
}
|
|
|
|
is_630 = of_device_is_compatible(pdev->dev.of_node,
|
|
"qcom,gpucc-sdm630");
|
|
if (is_630) {
|
|
gpu_pll0_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1]
|
|
= 1550000000;
|
|
gpu_pll1_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1]
|
|
= 1550000000;
|
|
/* Add new frequency table */
|
|
gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_630;
|
|
}
|
|
|
|
/* GFX rail fmax data linked to branch clock */
|
|
of_get_fmax_vdd_class(pdev, &gpucc_gfx3d_clk.clkr.hw,
|
|
"qcom,gfxfreq-corner", 1);
|
|
|
|
clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap,
|
|
&gpu_pll0_config);
|
|
clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap,
|
|
&gpu_pll0_config);
|
|
|
|
ret = qcom_cc_really_probe(pdev, &gpucc_660_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register GPUCC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
clk_prepare_enable(gpucc_cxo_clk.clkr.hw.clk);
|
|
|
|
dev_info(&pdev->dev, "Registered GPUCC clocks\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver gpucc_660_driver = {
|
|
.probe = gpucc_660_probe,
|
|
.driver = {
|
|
.name = "gpucc-sdm660",
|
|
.of_match_table = gpucc_660_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init gpucc_660_init(void)
|
|
{
|
|
return platform_driver_register(&gpucc_660_driver);
|
|
}
|
|
arch_initcall(gpucc_660_init);
|
|
|
|
static void __exit gpucc_660_exit(void)
|
|
{
|
|
platform_driver_unregister(&gpucc_660_driver);
|
|
}
|
|
module_exit(gpucc_660_exit);
|
|
|
|
/* GPU RBCPR Clocks */
|
|
static struct clk_regmap *gpucc_rbcpr_660_clocks[] = {
|
|
[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
|
|
[GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr,
|
|
};
|
|
|
|
static const struct qcom_cc_desc gpu_660_desc = {
|
|
.config = &gpucc_660_regmap_config,
|
|
.clks = gpucc_rbcpr_660_clocks,
|
|
.num_clks = ARRAY_SIZE(gpucc_rbcpr_660_clocks),
|
|
};
|
|
|
|
static const struct of_device_id gpucc_rbcpr_660_match_table[] = {
|
|
{ .compatible = "qcom,gpu-sdm660" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, gpucc_rbcpr_660_match_table);
|
|
|
|
static int gpu_660_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0;
|
|
|
|
struct regmap *regmap;
|
|
|
|
regmap = qcom_cc_map(pdev, &gpu_660_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
ret = qcom_cc_really_probe(pdev, &gpu_660_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register GPU RBCPR clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
|
|
dev_info(&pdev->dev, "Registered GPU RBCPR clocks\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver gpu_660_driver = {
|
|
.probe = gpu_660_probe,
|
|
.driver = {
|
|
.name = "gpu-sdm660",
|
|
.of_match_table = gpucc_rbcpr_660_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init gpu_660_init(void)
|
|
{
|
|
return platform_driver_register(&gpu_660_driver);
|
|
}
|
|
core_initcall(gpu_660_init);
|
|
|
|
static void __exit gpu_660_exit(void)
|
|
{
|
|
platform_driver_unregister(&gpu_660_driver);
|
|
}
|
|
module_exit(gpu_660_exit);
|
|
|