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69 lines
2.9 KiB
69 lines
2.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MACH_URQUELL_H
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#define __MACH_URQUELL_H
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/*
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* ------ 0x00000000 ------------------------------------
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* CS0 | (SW1,SW47) EEPROM, SRAM, NOR FLASH
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* -----+ 0x04000000 ------------------------------------
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* CS1 | (SW47) SRAM, SRAM-LAN-PCMCIA, NOR FLASH
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* -----+ 0x08000000 ------------------------------------
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* CS2 | DDR3
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* CS3 |
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* -----+ 0x10000000 ------------------------------------
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* CS4 | PCIe
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* -----+ 0x14000000 ------------------------------------
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* CS5 | (SW47) LRAM/URAM, SRAM-LAN-PCMCIA
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* -----+ 0x18000000 ------------------------------------
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* CS6 | ATA, NAND FLASH
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* -----+ 0x1c000000 ------------------------------------
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* CS7 | SH7786 register
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* -----+------------------------------------------------
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*/
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#define NOR_FLASH_ADDR 0x00000000
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#define NOR_FLASH_SIZE 0x04000000
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#define CS1_BASE 0x05000000
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#define CS5_BASE 0x15000000
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#define FPGA_BASE CS1_BASE
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#define BOARDREG(ofs) (FPGA_BASE + ofs##_OFS)
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#define UBOARDREG(ofs) (0xa0000000 + FPGA_BASE + ofs##_OFS)
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#define SRSTR_OFS 0x0000 /* System reset register */
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#define BDMR_OFS 0x0010 /* Board operating mode resister */
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#define IRL0SR_OFS 0x0020 /* IRL0 Status register */
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#define IRL0MSKR_OFS 0x0030 /* IRL0 Mask register */
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#define IRL1SR_OFS 0x0040 /* IRL1 Status register */
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#define IRL1MSKR_OFS 0x0050 /* IRL1 Mask register */
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#define IRL2SR_OFS 0x0060 /* IRL2 Status register */
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#define IRL2MSKR_OFS 0x0070 /* IRL2 Mask register */
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#define IRL3SR_OFS 0x0080 /* IRL3 Status register */
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#define IRL3MSKR_OFS 0x0090 /* IRL3 Mask register */
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#define SOFTINTR_OFS 0x0120 /* Softwear Interrupt register */
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#define SLEDR_OFS 0x0130 /* LED control resister */
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#define MAPSCIFSWR_OFS 0x0140 /* Map/SCIF Switch register */
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#define FPVERR_OFS 0x0150 /* FPGA Version register */
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#define FPDATER_OFS 0x0160 /* FPGA Date register */
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#define FPYEARR_OFS 0x0170 /* FPGA Year register */
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#define TCLKCR_OFS 0x0180 /* TCLK Control register */
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#define DIPSWMR_OFS 0x1000 /* DIPSW monitor register */
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#define FPODR_OFS 0x1010 /* Output port data register */
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#define ATACNR_OFS 0x1020 /* ATA-CN Control/status register */
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#define FPINDR_OFS 0x1030 /* Input port data register */
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#define MDSWMR_OFS 0x1040 /* MODE SW monitor register */
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#define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */
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#define SSICODECCR_OFS 0x1060 /* SSI-CODEC control register */
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#define PCIESLOTSR_OFS 0x1070 /* PCIexpress Slot status register */
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#define ETHERPORTSR_OFS 0x1080 /* EtherPhy Port status register */
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#define LATCHCR_OFS 0x3000 /* Latch control register */
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#define LATCUAR_OFS 0x3010 /* Latch upper address register */
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#define LATCLAR_OFS 0x3012 /* Latch lower address register */
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#define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
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#define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
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#define CHARLED_OFS 0x2000 /* Character LED */
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#endif /* __MACH_URQUELL_H */
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