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344 lines
16 KiB
344 lines
16 KiB
MSM SoC HSUSB controllers
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EHCI
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Required properties:
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- compatible: Should contain "qcom,ehci-host"
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- regs: offset and length of the register set in the memory map
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- usb-phy: phandle for the PHY device
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Example EHCI controller device node:
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ehci: ehci@f9a55000 {
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compatible = "qcom,ehci-host";
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reg = <0xf9a55000 0x400>;
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usb-phy = <&usb_otg>;
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};
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USB PHY with optional OTG:
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Required properties:
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- compatible: Should contain:
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"qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
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"qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
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"qcom,hsusb-otg" for chipsets with ChipIdea 45nm PHY
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- regs: Offset and length of the register set in the memory map
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- interrupts: interrupt-specifier for the OTG interrupt.
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- clocks: A list of phandle + clock-specifier pairs for the
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clocks listed in clock-names
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- clock-names: Should contain the following:
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"phy" USB PHY reference clock
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"core" Protocol engine clock
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"iface" Interface bus clock
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"alt_core" Protocol engine clock for targets with asynchronous
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reset methodology. (optional)
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- vdccx-supply: phandle to the regulator for the vdd supply for
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digital circuit operation.
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- v1p8-supply: phandle to the regulator for the 1.8V supply
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- v3p3-supply: phandle to the regulator for the 3.3V supply
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- resets: A list of phandle + reset-specifier pairs for the
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resets listed in reset-names
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- reset-names: Should contain the following:
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"phy" USB PHY controller reset
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"link" USB LINK controller reset
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- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
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1 - PHY control
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2 - PMIC control
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Optional properties:
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- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
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- switch-gpio: A phandle + gpio-specifier pair. Some boards are using Dual
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SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex
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D+/D- USB lines between connectors.
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- qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
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Mode Eye Diagram test. Start address at which these values will be
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written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
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"do not overwrite default value at this address".
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For example: qcom,phy-init-sequence = < -1 0x63 >;
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Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1.
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- qcom,phy-num: Select number of pyco-phy to use, can be one of
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0 - PHY one, default
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1 - Second PHY
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Some platforms may have configuration to allow USB
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controller work with any of the two HSPHYs present.
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- qcom,vdd-levels: This property must be a list of three integer values
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(no, min, max) where each value represents either a voltage
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in microvolts or a value corresponding to voltage corner.
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- qcom,manual-pullup: If present, vbus is not routed to USB controller/phy
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and controller driver therefore enables pull-up explicitly
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before starting controller using usbcmd run/stop bit.
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- extcon: phandles to external connector devices. First phandle
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should point to external connector, which provide "USB"
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cable events, the second should point to external connector
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device, which provide "USB-HOST" cable events. If one of
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the external connector devices is not required empty <0>
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phandle should be specified.
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Example HSUSB OTG controller device node:
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usb@f9a55000 {
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compatible = "qcom,usb-otg-snps";
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reg = <0xf9a55000 0x400>;
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interrupts = <0 134 0>;
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dr_mode = "peripheral";
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clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
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<&gcc GCC_USB_HS_AHB_CLK>;
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clock-names = "phy", "core", "iface";
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vddcx-supply = <&pm8841_s2_corner>;
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v1p8-supply = <&pm8941_l6>;
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v3p3-supply = <&pm8941_l24>;
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resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
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reset-names = "phy", "link";
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qcom,otg-control = <1>;
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qcom,phy-init-sequence = < -1 0x63 >;
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qcom,vdd-levels = <1 5 7>;
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};
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OTG:
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Required properties :
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- compatible : should be "qcom,hsusb-otg"
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- regs : Array of offset and length of the register sets in the memory map
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- reg-names : indicates various iomem resources passed by name. The possible
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strings in this field are:
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"core": USB controller register space. (Required)
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"tcsr": TCSR register for routing USB Controller signals to
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either picoPHY0 or picoPHY1. (Optional)
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"phy_csr": PHY Wrapper CSR register space. Provides register level
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interface through AHB2PHY for performing PHY related operations
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like retention and HV interrupts management.
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- interrupts: IRQ line
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- interrupt-names: OTG interrupt name(s) referenced in interrupts above
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HSUSB OTG expects "core_irq" which is IRQ line from CORE and
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"async_irq" from HSPHY for asynchronous wakeup events in LPM.
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optional ones are described in next section.
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- qcom,hsusb-otg-phy-type: PHY type can be one of
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1 - Chipidea PHY (obsolete)
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2 - Synopsis Pico PHY
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3 - Synopsis Femto PHY
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4 - QUSB ULPI PHY
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- qcom,hsusb-otg-mode: Operational mode. Can be one of
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1 - Peripheral only mode
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2 - Host only mode
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3 - OTG mode
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Based on the mode, OTG driver registers platform devices for
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gadget and host.
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- qcom,hsusb-otg-otg-control: OTG control (VBUS and ID notifications)
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can be one of
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1 - PHY control
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2 - PMIC control
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3 - User control (via debugfs)
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- <supply-name>-supply: handle to the regulator device tree node
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Required "supply-name" is "HSUSB_VDDCX" (when voting for VDDCX) or
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"hsusb_vdd_dig" (when voting for VDDCX Corner voltage),
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"HSUSB_1p8-supply" and "HSUSB_3p3-supply".
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- qcom,vdd-voltage-level: This property must be a list of three integer
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values (none, min, max) where each value represents either a voltage
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in microvolts or a value corresponding to voltage corner. If usb core
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supports svs, min value will have absolute SVS or SVS corner otherwise
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min value will have absolute nominal or nominal corner.
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- clocks: a list of phandles to the USB clocks. Usage is as per
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
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property.
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Required clocks:
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"core_clk": USB core clock that is required for data transfers.
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"iface_clk": USB core clock that is required for register access.
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Optional clocks:
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"sleep_clk": PHY sleep clock. Required for interrupts.
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"phy_reset_clk": PHY blocks asynchronous reset clock. Required
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for the USB block reset. It is a reset only clock.
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"phy_por_clk": Reset only clock for asserting/de-asserting
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PHY POR signal. Required for overriding PHY parameters.
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"phy_csr_clk": Required for accessing PHY CSR registers through
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AHB2PHY interface.
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"phy_ref_clk": Required when PHY have referance clock,
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"xo": XO clock. The source clock that is used as a reference clock
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to the PHY.
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"bimc_clk", "snoc_clk", "pcnoc_clk": bus voting clocks. Used to
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keep buses at a nominal frequency during USB peripheral
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mode for achieving max throughput.
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- qcom,max-nominal-sysclk-rate: Indicates maximum nominal frequency for which
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system clock should be voted whenever streaming mode is enabled.
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Optional properties :
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- interrupt-names : Optional interrupt resource entries are:
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"pmic_id_irq" : Interrupt from PMIC for external ID pin notification.
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"phy_irq" : Interrupt from PHY. Used for ID detection.
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- qcom,hsusb-otg-disable-reset: If present then core is RESET only during
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init, otherwise core is RESET for every cable disconnect as well
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- qcom,hsusb-otg-pnoc-errata-fix: If present then workaround for PNOC
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performance issue is applied which requires changing the mem-type
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attribute via VMIDMT.
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- qcom,hsusb-otg-default-mode: The default USB mode after boot-up.
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Applicable only when OTG is controlled by user. Can be one of
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0 - None. Low power mode
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1 - Peripheral
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2 - Host
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- qcom,hsusb-otg-phy-init-seq: PHY configuration sequence. val, reg pairs
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terminate with -1
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- qcom,hsusb-otg-power-budget: VBUS power budget in mA
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0 will be treated as 500mA
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- qcom,hsusb-otg-pclk-src-name: The source of pclk
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- Refer to "Documentation/devicetree/bindings/arm/msm/msm-bus.txt" for
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below optional properties:
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- qcom,msm-bus,name
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- qcom,msm-bus,num_cases - There are three valid cases for this: NONE, MAX
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and MIN bandwidth votes. Minimum two cases must be defined for
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both NONE and MAX votes. If MIN vote is different from NONE VOTE
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then specify third case for MIN VOTE. If explicit NOC clock rates
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are not specified then MAX value should be large enough to get
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desired BUS frequencies. In case explicit NOC clock rates are
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specified, peripheral mode bus bandwidth vote should be defined
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to vote for arbitrated bandwidth so that 60MHz frequency is met.
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- qcom,msm-bus,num_paths
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- qcom,msm-bus,vectors
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- qcom,hsusb-otg-lpm-on-dev-suspend: If present then USB enter to
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low power mode upon receiving bus suspend.
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- qcom,hsusb-otg-clk-always-on-workaround: If present then USB core clocks
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remain active upon receiving bus suspend and USB cable is connected.
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Used for allowing USB to respond for remote wakup.
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- qcom,hsusb-otg-delay-lpm: If present then USB core will wait one second
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after disconnect before entering low power mode.
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- <supply-name>-supply: handle to the regulator device tree node.
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Optional "supply-name" is "vbus_otg" to supply vbus in host mode.
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- qcom,dp-manual-pullup: If present, vbus is not routed to USB controller/phy
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and controller driver therefore enables pull-up explicitly before
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starting controller using usbcmd run/stop bit.
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- qcom,usb2-enable-hsphy2: If present then USB2 controller is connected to 2nd
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HSPHY.
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- qcom,hsusb-log2-itc: value of 2^(log2_itc-1) will be used as the
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interrupt threshold (ITC), when log2_itc is between 1 to 7.
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- qcom,hsusb-l1-supported: If present, the device supports l1 (Link power
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management).
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- qcom,no-selective-suspend: If present selective suspend is disabled on hub ports.
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- qcom,hsusb-otg-mpm-dpsehv-int: If present, indicates mpm interrupt to be
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configured for detection of dp line transition during VDD minimization.
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- qcom,hsusb-otg-mpm-dmsehv-int: If present, indicates mpm interrupt to be
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configured for detection of dm line transition during VDD minimization.
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- pinctrl-names : This should be defined if a target uses gpio and pinctrl framework.
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See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt.
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It should specify the names of the configs that pinctrl can install in driver
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Following are the pinctrl config that can be installed
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"hsusb_active" : Active configuration of pins, this should specify active
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config of vddmin gpio (if used) defined in their pin groups.
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"hsusb_sleep" : Disabled configuration of pins, this should specify sleep
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config of vddmin gpio (if used) defined in their pin groups.
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- qcom,hsusb-otg-vddmin-gpio = If present, indicates a gpio that will be used
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to supply voltage to the D+ line during VDD minimization and peripheral
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bus suspend. If not exists, then VDD minimization will not be allowed
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during peripheral bus suspend.
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- qcom,ahb-async-bridge-bypass: If present, indicates that enable AHB2AHB By Pass
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mode with device controller for better throughput. With this mode, USB Core
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runs using PNOC clock and synchronous to it. Hence it is must to have proper
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"qcom,msm-bus,vectors" to have high bus frequency. User shouldn't try to
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enable this feature without proper bus voting. When this feature is enabled,
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it is required to do HW reset during cable disconnect for host mode functionality
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working and hence need to disable qcom,hsusb-otg-disable-reset. With this feature
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enabled, USB HW has to vote for maximum PNOC frequency as USB HW cannot tolerate
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changes in PNOC frequency which results in USB functionality failure.
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- qcom,disable-retention-with-vdd-min: If present don't allow phy retention but allow
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vdd min.
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- qcom,usbin-vadc: Corresponding vadc device's phandle to read usbin voltage using VADC.
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This will be used to get value of usb power supply's VOLTAGE_NOW property.
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- qcom,usbid-gpio: This corresponds to gpio which is used for USB ID detection.
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- qcom,hub-reset-gpio: This corresponds to gpio which is used for HUB reset.
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- qcom,sw-sel-gpio: This corresponds to gpio which is used for switch select routing
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of D+/D- between the USB HUB and type B USB jack for peripheral mode.
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- qcom,bus-clk-rate: If present, indicates nominal bus frequency to be voted for
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bimc/snoc/pcnoc clock with usb cable connected. If AHB2AHB bypass is enabled,
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pcnoc value should be defined to very large number so that PNOC runs at max
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frequency. If 'qcom,default-mode-svs' is also set then two set of frequencies
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must be specified for SVS and NOM modes which user can change using sysfs node.
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- qcom,phy-dvdd-always-on: If present PHY DVDD is supplied by a always-on
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regulator unlike vddcx/vddmx. PHY can keep D+ pull-up and D+/D-
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pull-down resistors during peripheral and host bus suspend without
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any re-work.
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- qcom,emulation: Indicates that we are running on emulation platform.
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- qcom,boost-sysclk-with-streaming: If present, enable controller specific
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streaming feature. Also this flag can bump up usb system clock to max in streaming
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mode. This flag enables streaming mode for all compositions and is different from
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streaming-func property defined in android device node. Please refer Doumentation/
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devicetree/bindings/usb/android-dev.txt for details about "streaming-func" property.
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- qcom,axi-prefetch-enable: If present, AXI64 interface will be used for transferring data
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to/from DDR by controller.
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- qcom,enable-sdp-typec-current-limit: Indicates whether type-c current for SDP CHARGER to
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be limited.
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- qcom,enable-phy-id-pullup: If present, PHY can keep D+ pull-up resistor on USB ID line
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during cable disconnect.
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- qcom,max-svs-sysclk-rate: Indicates system clock frequency voted by driver in
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non-perf mode. In perf mode driver uses qcom,max-nominal-sysclk-rate.
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- qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs,
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which is used as a vote by driver to get max performance in perf mode.
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- qcom,default-mode-svs: Indicates USB system clock should run at SVS frequency.
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User can bump it up using 'perf_mode' sysfs attribute for gadget.
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- qcom,vbus-low-as-hostmode: If present, specifies USB_VBUS to switch to host mode
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if USB_VBUS is low or device mode if USB_VBUS is high.
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- qcom,usbeth-reset-gpio: If present then an external usb-to-eth is connected to
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the USB host controller and its RESET_N signal is connected to this
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usbeth-reset-gpio GPIO. It should be driven LOW to RESET the usb-to-eth.
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- qcom,enumeration-check-for-sdp: If present, start timer for SDP charger to check enumeration
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happen or not.
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Example HSUSB OTG controller device node :
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usb@f9690000 {
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compatible = "qcom,hsusb-otg";
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reg = <0xf9690000 0x400>;
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reg-names = "core";
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interrupts = <134>;
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interrupt-names = "core_irq";
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qcom,hsusb-otg-phy-type = <2>;
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qcom,hsusb-otg-mode = <1>;
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qcom,hsusb-otg-otg-control = <1>;
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qcom,hsusb-otg-disable-reset;
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qcom,hsusb-otg-pnoc-errata-fix;
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qcom,hsusb-otg-default-mode = <2>;
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qcom,hsusb-otg-phy-init-seq = <0x01 0x90 0xffffffff>;
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qcom,hsusb-otg-power-budget = <500>;
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qcom,hsusb-otg-pclk-src-name = "dfab_usb_clk";
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qcom,hsusb-otg-lpm-on-dev-suspend;
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qcom,hsusb-otg-clk-always-on-workaround;
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hsusb_vdd_dig-supply = <&pm8226_s1_corner>;
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HSUSB_1p8-supply = <&pm8226_l10>;
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HSUSB_3p3-supply = <&pm8226_l20>;
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qcom,vdd-voltage-level = <1 5 7>;
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qcom,dp-manual-pullup;
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qcom,hsusb-otg-mpm-dpsehv-int = <49>;
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qcom,hsusb-otg-mpm-dmsehv-int = <58>;
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qcom,max-nominal-sysclk-rate = <133330000>;
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qcom,max-svs-sysclk-rate = <100000000>;
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qcom,pm-qos-latency = <59>;
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qcom,msm-bus,name = "usb2";
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qcom,msm-bus,num_cases = <2>;
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qcom,msm-bus,num_paths = <1>;
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qcom,msm-bus,vectors =
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<87 512 0 0>,
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<87 512 60000000 960000000>;
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pinctrl-names = "hsusb_active","hsusb_sleep";
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pinctrl-0 = <&vddmin_act>;
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pinctrl-0 = <&vddmin_sus>;
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qcom,hsusb-otg-vddmin-gpio = <&pm8019_mpps 6 0>;
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qcom,disable-retention-with-vdd-min;
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qcom,usbin-vadc = <&pm8226_vadc>;
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qcom,usbid-gpio = <&msm_gpio 110 0>;
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};
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