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41 lines
1.8 KiB
41 lines
1.8 KiB
* MSM Serial UART for GENI based cores.
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The MSM serial UART driver supports low speed and high speed use-cases.
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This is meant only for QUPv3 GENI based cores and isn't backwards compatible.
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There is support for console usecases and for higher speed usecases that need
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DMA.
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Required properties:
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- compatible: should contain "qcom,msm-geni-uart, qcom,msm-geni-console"
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for UART console usecases, "qcom,msm-geni-uart, qcom,msm-geni-serial-hs"
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for High Speed (HS) usecases.
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- reg: Should contain UART register location and length.
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- interrupts: Should contain UART core interrupts.
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- clocks: clocks needed for UART, includes the core and AHB clock.
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- pinctrl-names/pinctrl-0/1/2: The GPIOs assigned to this core. The names
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should be "default", "active" and "sleep" for the pin confuguration.
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It should be in "default" for the default pin configuration during probe,
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in "active" when core is active or in "sleep" when entering in sleep state.
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- qcom,wrapper-core: Wrapper QUPv3 core containing this UART controller.
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Optional properties:
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- qcom,wakeup-byte: Byte to be injected in the tty layer during wakeup isr.
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- qcom,auto-suspend-disable: Disable PM runtime API's and make vote clock on/off
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optional and rely on system suspend/resume.
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Example:
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qupv3_uart11: qcom,qup_uart@0xa88000 {
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compatible = "qcom,msm-geni-uart";
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reg = <0xa88000 0x7000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "active", "sleep";
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pinctrl-0 = <&qup_1_uart_3_default>;
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pinctrl-1 = <&qup_1_uart_3_active>;
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pinctrl-2 = <&qup_1_uart_3_sleep>;
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interrupts = <0 355 0>;
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qcom,wrapper-core = <&qupv3_0>;
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qcom,wakeup-byte = <0xFF>;
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};
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