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96 lines
4.7 KiB
96 lines
4.7 KiB
QTI Global Distributed Switch Controller (GDSC) Regulator Driver
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The GDSC driver, implemented under the regulator framework, is responsible for
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safely collapsing and restoring power to peripheral and multimedia cores on
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chipsets like SDM845 for power savings.
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Required properties:
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- compatible: Must be "qcom,gdsc"
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- regulator-name: A string used as a descriptive name for regulator outputs
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- reg: The address of the GDSCR register
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Optional properties:
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- parent-supply: phandle to the parent supply/regulator node
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- clock-names: List of string names for core clocks
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- qcom,retain-mem: Presence denotes a hardware requirement to leave the
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forced core memory retention signals in the core's clock
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branch control registers asserted.
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- qcom,retain-periph: Presence denotes a hardware requirement to leave the
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forced periph memory retention signal in the core's clock
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branch control registers asserted.
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- qcom,skip-logic-collapse: Presence denotes a requirement to leave power to
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the core's logic enabled.
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- qcom,support-hw-trigger: Presence denotes a hardware feature to switch
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on/off this regulator based on internal HW signals
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to save more power.
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- qcom,enable-root-clk: Presence denotes that the clocks in the "clocks"
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property are required to be enabled before gdsc is
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turned on and disabled before turning off gdsc. This
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will be used in subsystems where reset is synchronous
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and root clk is active without sw being aware of its
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state. The clock-name which denotes the root clock
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should be named as "core_root_clk".
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- qcom,force-enable-root-clk: If set, denotes that the root clock should be
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force enabled before turning on the GDSC and then be
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immediately force disabled. Likewise for GDSC disable.
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This is used in cases where the core root clock needs
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to be force-enabled prior to turning on the core. The
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clock-name which denotes the root clock should be
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"core_root_clk".
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- qcom,clk-dis-wait-val: Input value for CLK_DIS_WAIT controls state transition
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delay after halting clock in the collapsible core.
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- reg-names: Names of the bases for the above "reg" registers.
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Ex. "base", "domain-addr", "sw-reset", "hw-ctrl-addr".
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- qcom,no-status-check-on-disable: Do not poll the status bit when GDSC
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is disabled.
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- qcom,skip-disable: Boolean flag indicating that the GDSC must not be
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physically disabled upon a software disable request.
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Instead, the GDSC will be disabled by the always-on
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processor (AOP) upon entering system sleep. The AOP
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will also perform a special reset sequence for the GDSC
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upon resuming from system sleep.
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- qcom,disallow-clear: Presence denotes the periph & core memory will not be
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cleared, unless the required subsystem does not invoke
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the api which will allow clearing the bits.
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- qcom,gds-timeout: Maximum time (in usecs) that might be taken by a GDSC
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to enable.
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- qcom,reset-aon-logic: If present, the GPU DEMET cells need to be reset while
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enabling the GX GDSC.
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- vdd_parent-supply: phandle to the regulator that this GDSC gates. If
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present, need to vote for a minimum operational voltage
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(LOW_SVS) on the GDSC parent regulator prior to
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configuring it. The vote is removed once the GDSC FSM
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has latched on to the new state.
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- resets: reset specifier pair consisting of phandle for the reset controller
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and reset lines used by this controller. These can be
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supplied only if we support qcom,skip-logic-collapse.
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- reset-names: reset signal name strings sorted in the same order as the resets
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property. These can be supplied only if we support
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qcom,skip-logic-collapse.
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- qcom,msm-bus,name: Name to use for the bus client. See [1] for details.
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- qcom,msm-bus,num-cases: Must be 2 if qcom,msm-bus,name is specified. The
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first case corresponds to no bus request and the second
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case corresponds to a minimum bus request. See [1] for
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details.
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- qcom,msm-bus,num-paths: Should be 1 if qcom,msm-bus,name is specified. See
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[1] for details.
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- qcom,msm-bus,vectors-KBps: Required if qcom,msm-bus,name is specified. See
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[1] for an explanation of the data format.
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- mboxes: Mailbox tuple containing QMP mailbox phandle and channel
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identifier. If this is specified, then a QMP message
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should be sent to enable the GDSC instead of setting
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SW_COLLAPSE=0.
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- qcom,skip-disable-before-sw-enable: Presence denotes a hardware requirement
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to leave the GDSC on that has been
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enabled by an entity external to HLOS.
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[1]: Documentation/devicetree/bindings/arm/msm/msm_bus.txt
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Example:
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gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_oxili_gx";
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parent-supply = <&pm8841_s4>;
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reg = <0xfd8c4024 0x4>;
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clock-names = "core_clk";
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};
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