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181 lines
8.4 KiB
181 lines
8.4 KiB
Qualcomm Technologies, Inc. Standard Secure Digital Host Controller (SDHC)
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Secure Digital Host Controller provides standard host interface to SD/MMC/SDIO cards.
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Required properties:
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- compatible : should be "qcom,sdhci-msm"
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For SDCC version 5.0.0, MCI registers are removed from SDCC interface
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and some registers are moved to HC. New compatible string is added to
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support this change - "qcom,sdhci-msm-v5".
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- reg : should contain SDHC, SD Core register map.
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- reg-names : indicates various resources passed to driver (via reg proptery) by name.
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Required "reg-names" are "hc_mem" and "core_mem"
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optional ones are "tlmm_mem"
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- interrupts : should contain SDHC interrupts.
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- interrupt-names : indicates interrupts passed to driver (via interrupts property) by name.
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Required "interrupt-names" are "hc_irq" and "pwr_irq".
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- <supply-name>-supply: phandle to the regulator device tree node
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Required "supply-name" are "vdd" and "vdd-io".
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Required alias:
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- The slot number is specified via an alias with the following format
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'sdhc{n}' where n is the slot number.
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Optional Properties:
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- interrupt-names - "status_irq". This status_irq will be used for card
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detection.
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- qcom,bus-width - defines the bus I/O width that controller supports.
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Units - number of bits. The valid bus-width values are
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1, 4 and 8.
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- qcom,nonremovable - specifies whether the card in slot is
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hot pluggable or hard wired.
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- qcom,nonhotplug - specifies the card in slot is not hot pluggable.
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if card lost or removed manually at runtime, don't retry
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to redetect it until next reboot probe.
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- qcom,bus-speed-mode - specifies supported bus speed modes by host.
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The supported bus speed modes are :
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"HS200_1p8v" - indicates that host can support HS200 at 1.8v.
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"HS200_1p2v" - indicates that host can support HS200 at 1.2v.
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"DDR_1p8v" - indicates that host can support DDR mode at 1.8v.
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"DDR_1p2v" - indicates that host can support DDR mode at 1.2v.
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- qcom,bus-aggr-clk-rates: this is an array that specifies the frequency for
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the bus-aggr-clk which should be set corresponding to the
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frequency used from clk-rate. The Frequency of this clock
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should be decided based on the power mode in which the
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apps clk would run with frequency in clk-rates.
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- qcom,devfreq,freq-table - specifies supported frequencies for clock scaling.
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Clock scaling logic shall toggle between these frequencies based
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on card load. In case the defined frequencies are over or below
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the supported card frequencies, they will be overridden
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during card init. In case this entry is not supplied,
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the driver will construct one based on the card
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supported max and min frequencies.
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The frequencies must be ordered from lowest to highest.
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- qcom,pm-qos-irq-type - the PM QoS request type to be used for IRQ voting.
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Can be either "affine_cores" or "affine_irq". If not specified, will default
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to "affine_cores". Use "affine_irq" setting in case an IRQ balancer is active,
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and IRQ affinity changes during runtime.
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- qcom,pm-qos-irq-cpu - specifies the CPU for which IRQ voting shall be done.
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If "affine_cores" was specified for property 'qcom,pm-qos-irq-type'
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then this property must be defined, and is not relevant otherwise.
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- qcom,pm-qos-irq-latency - a tuple defining two latency values with which
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PM QoS IRQ voting shall be done. The first value is the latecy to be used
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when load is high (performance mode) and the second is for low loads
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(power saving mode).
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- qcom,pm-qos-cpu-groups - defines cpu groups mapping.
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Each cell represnets a group, which is a cpu bitmask defining which cpus belong
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to that group.
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- qcom,pm-qos-<mode>-latency-us - where <mode> is either "cmdq" or "legacy".
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An array of latency value tuples, each tuple corresponding to a cpu group in the order
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defined in property 'qcom,pm-qos-cpu-groups'. The first value is the latecy to be used
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when load is high (performance mode) and the second is for low loads
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(power saving mode). These values will be used for cpu group voting for
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command-queueing mode or legacy respectively.
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- qcom,core_3_0v_support: an optional property that is used to fake
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3.0V support for SDIO devices.
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- qcom,scaling-lower-bus-speed-mode: specifies the lower bus speed mode to be used
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during clock scaling. If this property is not
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defined, then it falls back to the default HS
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bus speed mode to maintain backward compatibility.
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- qcom,sdr104-wa: On Certain chipsets, SDR104 mode might be unstable causing CRC errors
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on the interface. So there is a workaround implemented to skip printing
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register dumps on CRC errors and also downgrade bus speed mode to
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SDR50/DDR50 in case of continuous CRC errors. Set this flag to enable
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this workaround.
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- qcom,restore-after-cx-collapse - specifies whether the SDCC registers contents need
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to be saved and restored by software when the CX Power Collapse feature is enabled.
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On certain chipsets, coming out of the CX Power Collapse event, the SDCC registers
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contents will not be retained. It is software responsibility to restore the
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SDCC registers before resuming to normal operation.
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- qcom,force-sdhc1-probe: Force probing sdhc1 even if it is not the boot device.
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- qcom,dll-hsr-list: List of DLL-HSR values which are tuned for given process-node
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and platform. The sequence of values in this list must follow the
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sequence listed in sdhci_msm_dll_hsr data structure.
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In the following, <supply> can be vdd (flash core voltage) or vdd-io (I/O voltage).
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- qcom,<supply>-always-on - specifies whether supply should be kept "on" always.
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- qcom,<supply>-lpm_sup - specifies whether supply can be kept in low power mode (lpm).
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- qcom,<supply>-voltage_level - specifies voltage levels for supply. Should be
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specified in pairs (min, max), units uV.
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- qcom,<supply>-current_level - specifies load levels for supply in lpm or
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high power mode (hpm). Should be specified in
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pairs (lpm, hpm), units uA.
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- gpios - specifies gpios assigned for sdhc slot.
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- qcom,gpio-names - a list of strings that map in order to the list of gpios
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Tlmm pins are specified as <clk cmd data> and starting with eMMC5.0 as
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<clk cmd data rclk>
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- Refer to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt"
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for following optional properties:
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- pinctrl-names
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- pinctrl-0, pinctrl-1,.. pinctrl-n
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- qcom,large-address-bus - specifies whether the soc is capable of
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supporting larger than 32 bit address bus width.
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- qcom,wakeup-on-idle: if configured, the mmcqd thread will call
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set_wake_up_idle(), thereby voting for it to be called on idle CPUs.
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- qcom,wakeup-on-idle: if configured, the mmcqd thread will call
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set_wake_up_idle(), thereby voting for it to be called on idle CPUs.
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Example:
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aliases {
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sdhc1 = &sdhc_1;
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};
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sdhc_1: qcom,sdhc@f9824900 {
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compatible = "qcom,sdhci-msm";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 123 0>, <0 138 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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vdd-supply = <&pm8941_l21>;
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vdd-io-supply = <&pm8941_l13>;
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qcom,vdd-voltage-level = <2950000 2950000>;
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qcom,vdd-current-level = <9000 800000>;
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qcom,vdd-io-always-on;
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qcom,vdd-io-lpm-sup;
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qcom,vdd-io-voltage-level = <1800000 2950000>;
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qcom,vdd-io-current-level = <6 22000>;
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qcom,devfreq,freq-table = <52000000 200000000>;
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qcom,devfreq,freq-table = <52000000 200000000>;
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pinctrl-names = "active", "sleep";
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pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
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pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_on &sdc1_data_on>;
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qcom,bus-width = <4>;
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qcom,nonremovable;
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qcom,large-address-bus;
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qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
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qcom,scaling-lower-bus-speed-mode = "DDR52";
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gpios = <&msmgpio 40 0>, /* CLK */
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<&msmgpio 39 0>, /* CMD */
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<&msmgpio 38 0>, /* DATA0 */
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<&msmgpio 37 0>, /* DATA1 */
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<&msmgpio 36 0>, /* DATA2 */
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<&msmgpio 35 0>; /* DATA3 */
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qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
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qcom,pm-qos-irq-type = "affine_cores";
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qcom,pm-qos-irq-cpu = <0>;
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qcom,pm-qos-irq-latency = <500 100>;
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qcom,pm-qos-cpu-groups = <0x03 0x0c>;
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qcom,pm-qos-cmdq-latency-us = <50 100>, <50 100>;
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qcom,pm-qos-legacy-latency-us = <50 100>, <50 100>;
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};
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sdhc_2: qcom,sdhc@f98a4900 {
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qcom,pm-qos-irq-type = "affine_irq";
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qcom,pm-qos-irq-latency = <120 200>;
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};
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