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103 lines
3.1 KiB
103 lines
3.1 KiB
OMAP HS USB Host
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Required properties:
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- compatible: should be "ti,usbhs-host"
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- reg: should contain one register range i.e. start and length
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- ti,hwmods: must contain "usb_host_hs"
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Optional properties:
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- num-ports: number of USB ports. Usually this is automatically detected
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from the IP's revision register but can be overridden by specifying
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this property. A maximum of 3 ports are supported at the moment.
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- portN-mode: String specifying the port mode for port N, where N can be
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from 1 to 3. If the port mode is not specified, that port is treated
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as unused. When specified, it must be one of the following.
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"ehci-phy",
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"ehci-tll",
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"ehci-hsic",
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"ohci-phy-6pin-datse0",
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"ohci-phy-6pin-dpdm",
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"ohci-phy-3pin-datse0",
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"ohci-phy-4pin-dpdm",
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"ohci-tll-6pin-datse0",
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"ohci-tll-6pin-dpdm",
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"ohci-tll-3pin-datse0",
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"ohci-tll-4pin-dpdm",
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"ohci-tll-2pin-datse0",
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"ohci-tll-2pin-dpdm",
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- single-ulpi-bypass: Must be present if the controller contains a single
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ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
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- clocks: a list of phandles and clock-specifier pairs, one for each entry in
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clock-names.
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- clock-names: should include:
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For OMAP3
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* "usbhost_120m_fck" - 120MHz Functional clock.
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For OMAP4+
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* "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
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* "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
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* "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
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* "utmi_p1_gfclk" - Port 1 UTMI clock mux.
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* "utmi_p2_gfclk" - Port 2 UTMI clock mux.
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* "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
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* "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
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* "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
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* "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
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* "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
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* "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
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* "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
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* "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
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* "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
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Required properties if child node exists:
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- #address-cells: Must be 1
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- #size-cells: Must be 1
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- ranges: must be present
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Properties for children:
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The OMAP HS USB Host subsystem contains EHCI and OHCI controllers.
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See Documentation/devicetree/bindings/usb/ehci-omap.txt and
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Documentation/devicetree/bindings/usb/ohci-omap3.txt.
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Example for OMAP4:
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usbhshost: usbhshost@4a064000 {
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compatible = "ti,usbhs-host";
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reg = <0x4a064000 0x800>;
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ti,hwmods = "usb_host_hs";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usbhsohci: ohci@4a064800 {
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compatible = "ti,ohci-omap3", "usb-ohci";
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reg = <0x4a064800 0x400>;
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interrupt-parent = <&gic>;
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interrupts = <0 76 0x4>;
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};
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usbhsehci: ehci@4a064c00 {
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compatible = "ti,ehci-omap", "usb-ehci";
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reg = <0x4a064c00 0x400>;
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interrupt-parent = <&gic>;
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interrupts = <0 77 0x4>;
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};
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};
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&usbhshost {
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port1-mode = "ehci-phy";
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port2-mode = "ehci-tll";
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port3-mode = "ehci-phy";
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};
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&usbhsehci {
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phys = <&hsusb1_phy 0 &hsusb3_phy>;
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};
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