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137 lines
4.4 KiB
137 lines
4.4 KiB
======================================================================
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Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
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======================================================================
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The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
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peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
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primary use case of the Aspeed LPC controller is as a slave on the bus
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(typically in a Baseboard Management Controller SoC), but under certain
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conditions it can also take the role of bus master.
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The LPC controller is represented as a multi-function device to account for the
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mix of functionality it provides. The principle split is between the register
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layout at the start of the I/O space which is, to quote the Aspeed datasheet,
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"basically compatible with the [LPC registers from the] popular BMC controller
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H8S/2168[1]", and everything else, where everything else is an eclectic
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collection of functions with a esoteric register layout. "Everything else",
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here labeled the "host" portion of the controller, includes, but is not limited
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to:
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* An IPMI Block Transfer[2] Controller
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* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
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physical properties of some LPC pins, configuration of serial IRQs, and
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APB-to-LPC bridging amonst other functions.
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* An LPC Host Interface Controller: Manages functions exposed to the host such
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as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
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management and bus snoop configuration.
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* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
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hardware management protocols for handover between the host and baseboard
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management controller.
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Additionally the state of the LPC controller influences the pinmux
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configuration, therefore the host portion of the controller is exposed as a
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syscon as a means to arbitrate access.
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[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
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[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
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[2] http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
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[3] https://en.wikipedia.org/wiki/Super_I/O
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Required properties
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===================
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- compatible: One of:
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"aspeed,ast2400-lpc", "simple-mfd"
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"aspeed,ast2500-lpc", "simple-mfd"
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- reg: contains the physical address and length values of the Aspeed
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LPC memory region.
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- #address-cells: <1>
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- #size-cells: <1>
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- ranges: Maps 0 to the physical address and length of the LPC memory
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region
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Required LPC Child nodes
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========================
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BMC Node
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--------
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- compatible: One of:
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"aspeed,ast2400-lpc-bmc"
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"aspeed,ast2500-lpc-bmc"
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- reg: contains the physical address and length values of the
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H8S/2168-compatible LPC controller memory region
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Host Node
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---------
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- compatible: One of:
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"aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
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"aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
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- reg: contains the address and length values of the host-related
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register space for the Aspeed LPC controller
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- #address-cells: <1>
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- #size-cells: <1>
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- ranges: Maps 0 to the address and length of the host-related LPC memory
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region
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Example:
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lpc: lpc@1e789000 {
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compatible = "aspeed,ast2500-lpc", "simple-mfd";
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reg = <0x1e789000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1e789000 0x1000>;
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lpc_bmc: lpc-bmc@0 {
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compatible = "aspeed,ast2500-lpc-bmc";
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reg = <0x0 0x80>;
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};
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lpc_host: lpc-host@80 {
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compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
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reg = <0x80 0x1e0>;
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reg-io-width = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80 0x1e0>;
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};
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};
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Host Node Children
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==================
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LPC Host Controller
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-------------------
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The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
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between the host and the baseboard management controller. The registers exist
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in the "host" portion of the Aspeed LPC controller, which must be the parent of
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the LPC host controller node.
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Required properties:
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- compatible: One of:
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"aspeed,ast2400-lhc";
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"aspeed,ast2500-lhc";
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- reg: contains offset/length values of the LHC memory regions. In the
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AST2400 and AST2500 there are two regions.
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Example:
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lhc: lhc@20 {
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compatible = "aspeed,ast2500-lhc";
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reg = <0x20 0x24 0x48 0x8>;
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};
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