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263 lines
10 KiB
263 lines
10 KiB
* ARM System MMU Architecture Implementation
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ARM SoCs may contain an implementation of the ARM System Memory
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Management Unit Architecture, which can be used to provide 1 or 2 stages
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of address translation to bus masters external to the CPU.
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The SMMU may also raise interrupts in response to various fault
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conditions.
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** System MMU required properties:
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- compatible : Should be one of:
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"arm,smmu-v1"
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"arm,smmu-v2"
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"arm,mmu-400"
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"arm,mmu-401"
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"arm,mmu-500"
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"cavium,smmu-v2"
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"qcom,smmu-v2"
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"qcom,qsmmu-v500"
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depending on the particular implementation and/or the
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version of the architecture implemented.
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- reg : Base address and size of the SMMU.
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- reg-names : For the "qcom,qsmmu-v500" device "tcu-base" is expected.
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- #global-interrupts : The number of global interrupts exposed by the
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device.
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- interrupts : Interrupt list, with the first #global-irqs entries
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corresponding to the global interrupts and any
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following entries corresponding to context interrupts,
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specified in order of their indexing by the SMMU.
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For SMMUv2 implementations, there must be exactly one
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interrupt per context bank. In the case of a single,
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combined interrupt, it must be listed multiple times.
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- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
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for details. With a value of 1, each "iommus" entry
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represents a distinct stream ID emitted by that device
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into the relevant SMMU.
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SMMUs with stream matching support and complex masters
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may use a value of 2, where the second cell represents
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an SMR mask to combine with the ID in the first cell.
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Care must be taken to ensure the set of matched IDs
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does not result in conflicts.
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** System MMU optional properties:
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- dma-coherent : Present if page table walks made by the SMMU are
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cache coherent with the CPU.
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NOTE: this only applies to the SMMU itself, not
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masters connected upstream of the SMMU.
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- calxeda,smmu-secure-config-access : Enable proper handling of buggy
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implementations that always use secure access to
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SMMU configuration registers. In this case non-secure
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aliases of secure registers have to be used during
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SMMU configuration.
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- attach-impl-defs : global registers to program at device attach
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time. This should be a list of 2-tuples of the format:
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<offset reg_value>.
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- qcom,fatal-asf : Enable BUG_ON for address size faults. Some hardware
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requires special fixups to recover from address size
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faults. Rather than applying the fixups just BUG since
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address size faults are due to a fundamental programming
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error from which we don't care about recovering anyways.
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- qcom,tz-device-id : A string indicating the device ID for this SMMU known
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to TZ. See msm_tz_smmu.c for a full list of mappings.
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- qcom,skip-init : Disable resetting configuration for all context banks
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during device reset. This is useful for targets where
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some context banks are dedicated to other execution
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environments outside of Linux and those other EEs are
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programming their own stream match tables, SCTLR, etc.
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Without setting this option we will trample on their
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configuration.
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- qcom,dynamic : Allow dynamic domains to be attached. This is only
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useful if the upstream hardware is capable of switching
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between multiple domains within a single context bank.
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- qcom,use-3-lvl-tables:
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Some hardware configurations may not be optimized for using
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a four level page table configuration. Set to use a three
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level page table instead.
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- qcom,no-asid-retention:
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Some hardware may lose internal state for asid after
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retention. No cache invalidation operations involving asid
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may be used.
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- qcom,actlr:
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An array of <sid mask actlr-setting>.
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Any sid X for which X&~mask==sid will be programmed with the
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given actlr-setting.
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- qcom,enable-static-cb : Enables option to use pre-defined static context bank
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allocation programmed by TZ. Global register including SMR and
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S2CR registers are configured by TZ before kernel comes up and
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this programming is not altered throughout the life of system.
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We would be reading through these registers at run time to
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identify CB allocated for a particular sid. SID masking isn't
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supported as we are directly comparing client SID with ID bits
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of SMR registers.
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-qcom,disable-atos:
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Some hardware may not have full support for atos debugging
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in tandem with other features like power collapse.
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-qcom,opt-out-tbu-halting:
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Allow certain TBUs to opt-out from being halted for the
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ATOS operation to proceed. Halting certain TBUs would cause
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considerable impact to the system such as deadlocks on demand.
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Such TBUs can be opted out to be halted from software.
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- qcom,deferred-regulator-disable-delay : The time delay for deferred regulator
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disable in ms. In case of unmap call, regulator is
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enabled/disabled. This may introduce additional delay. For
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clients who do not detach, it's not possible to keep regulator
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vote while smmu is attached. Type is <u32>.
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- qcom,min-iova-align:
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Some hardware revision might have the deep prefetch bug where
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invalid entries in the prefetch window would cause improper
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permissions to be cached for the valid entries in this window.
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Enable the workaround on such hardware by aligning the start
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and end of all mapped buffers to prefetch size boundary, which
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is defined by ARM_SMMU_MIN_IOVA_ALIGN.
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- qcom,no-dynamic-asid:
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Clients that uses the dynamic domains will have an unique asid
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per each domain and all domains can share the same context bank.
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When ASID based invalidation is used, on some hardware revisions,
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as a result of multiple ASID's associated with the same context
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bank, TLB entries are not invalidated properly. On such systems,
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we can choose to have a single ASID associated with all domains
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for a context bank.
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- qcom,testbus-version:
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Testbus implementation is different in some hardware for eg some doesn't
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have a separate register for programming tbu testbuses so, they share the
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same register to program both tcu and tbu testbuses. on such hardware this
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option can be used to specify the testbus version to support testbus interface.
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Type is <u32>.
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- clocks : List of clocks to be used during SMMU register access. See
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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for information about the format. For each clock specified
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here, there must be a corresponding entry in clock-names
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(see below).
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- clock-names : List of clock names corresponding to the clocks specified in
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the "clocks" property (above). See
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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for more info.
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- (%s)-supply : Phandle of the regulator that should be powered on during
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SMMU register access. (%s) is a string from the
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qcom,regulator-names property.
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- qcom,regulator-names :
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List of strings to use with the (%s)-supply property.
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- qcom,msm-bus,name
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- qcom,msm-bus,num-cases
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- qcom,msm-bus,num-paths
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- qcom,msm-bus,vectors-KBps
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: Refer to devicetree/bindings/arm/msm/msm_bus.txt
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** Deprecated properties:
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- mmu-masters (deprecated in favour of the generic "iommus" binding) :
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A list of phandles to device nodes representing bus
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masters for which the SMMU can provide a translation
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and their corresponding Stream IDs. Each device node
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linked from this list must have a "#stream-id-cells"
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property, indicating the number of Stream ID
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arguments associated with its phandle.
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** Examples:
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/* SMMU with stream matching or stream indexing */
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smmu1: iommu {
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compatible = "arm,smmu-v1";
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reg = <0xba5e0000 0x10000>;
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#global-interrupts = <2>;
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interrupts = <0 32 4>,
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<0 33 4>,
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<0 34 4>, /* This is the first context interrupt */
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<0 35 4>,
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<0 36 4>,
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<0 37 4>;
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#iommu-cells = <1>;
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};
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/* device with two stream IDs, 0 and 7 */
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master1 {
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iommus = <&smmu1 0>,
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<&smmu1 7>;
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};
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/* SMMU with stream matching */
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smmu2: iommu {
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...
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#iommu-cells = <2>;
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};
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/* device with stream IDs 0 and 7 */
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master2 {
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iommus = <&smmu2 0 0>,
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<&smmu2 7 0>;
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};
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/* device with stream IDs 1, 17, 33 and 49 */
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master3 {
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iommus = <&smmu2 1 0x30>;
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};
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* Qualcomm MMU-500 TBU Device
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The qcom,qsmmu-v500 device implements a number of register regions containing
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debug functionality. Each register region maps to a separate tbu from the
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arm mmu-500 implementation.
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** TBU required properties:
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- compatible : Should be one of:
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"qcom,qsmmuv500-tbu"
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- reg : Base address and size.
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- reg-names : "base" and "status-reg" are expected
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"base" is the main TBU register region.
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"status-reg" indicates whether hw can process a new request.
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-qcom,stream-id-range:
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Pair of values describing the smallest supported stream-id
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and the size of the entire set.
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Example:
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smmu {
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compatible = "qcom,qsmmu-v500";
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tbu@0x1000 {
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compatible = "qcom,qsmmuv500-tbu";
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regs = <0x1000 0x1000>,
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<0x2000 0x8>;
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reg-names = "base",
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"status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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};
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};
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