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37 lines
1.1 KiB
37 lines
1.1 KiB
* ARC-HS Interrupt Distribution Unit
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This optional 2nd level interrupt controller can be used in SMP configurations for
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dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
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Properties:
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- compatible: "snps,archs-idu-intc"
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- interrupt-controller: This is an interrupt controller.
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- interrupt-parent: <reference to parent core intc>
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- #interrupt-cells: Must be <1>.
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Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
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of the particular interrupt line of IDU corresponds to the line N+24 of the
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core interrupt controller.
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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Example:
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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#interrupt-cells = <1>;
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};
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some_device: serial@c0fc1000 {
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interrupt-parent = <&idu_intc>;
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interrupts = <0>; /* upstream idu IRQ #24 */
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};
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