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87 lines
2.8 KiB
87 lines
2.8 KiB
QTI PDC interrupt controller
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PDC is QTI's platform parent interrupt controller that serves as wakeup source.
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Newer QTI SOCs are replacing MPM (MSM sleep Power Manager) with PDC (Power
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Domain Controller) to manage subsystem wakeups and resources during sleep.
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This driver marks the wakeup interrupts in APSS PDC such that it monitors the
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interrupts when the system is asleep, wakes up the APSS when one of these
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interrupts occur and replays it to the subsystem interrupt controller after it
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becomes operational.
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Earlier MPM architecture used arch-extension of GIC interrupt
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controller to mark enabled wake-up interrupts and monitor these when the
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system goes to sleep. Since the arch-extensions are no-longer available
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on newer kernel versions, this driver is implemented as hierarchical irq
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domain. GIC is parent interrupt controller at the highest level.
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Platform interrupt controller PDC is next in hierarchy, followed by others.
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This driver only configures the interrupts, does not handle them.
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PDC interrupt configuration involves programming of 2 set of registers:
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IRQ_ENABLE_BANK - Enable the irq
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IRQ_i_CFG - Configure the interrupt i
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Properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: Should contain one of -
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"qcom,pdc-sdm845",
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"qcom,pdc-sdmmagpie",
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"qcom,pdc-sm6150",
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"qcom,pdc-sm8150",
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"qcom,pdc-sdxprairie",
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"qcom,pdc-atoll",
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"qcom,pdc-virt"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Specifies the base physical address for PDC hardware
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block for DRV2.
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- interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: Specifies the number of cells needed to encode an interrupt source.
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Value must be 3.
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The encoding of these cells are same as described in
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Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
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- interrupt-parent:
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Usage: required
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Value type: <phandle>
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Definition: Specifies the interrupt parent necessary for hierarchical domain to operate.
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- interrupt-controller:
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Usage: required
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Value type: <bool>
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Definition: Identifies the node as an interrupt controller.
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- qcom,pdc-pins:
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Usage: optional
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Value type: <u32 array>
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Definition: Specifies the PDC pin and its mapping hwirq.
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The first element of the tuple is the PDC port.
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The second element is the GIC hwirq number for the PDC port.
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Usage is required when using "qcom,pdc-virt" as compatible.
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Example:
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pdcgic: interrupt-controller@0xb220000{
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compatible = "qcom,pdc-sdm845";
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reg = <0xb220000 0x30000>;
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#interrupt-cells = <3>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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pdcgic: interrupt-controller@0xb220000{
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compatible = "qcom,pdc-virt";
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reg = <0xb220000 0x30000>;
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#interrupt-cells = <3>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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qcom,pdc-pins = <8 520>, <9 521>;
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};
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