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kernel_samsung_sm7125/Documentation/devicetree/bindings/gpu/adreno-pwrlevels.txt

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Qualcomm Technologies, Inc. GPU powerlevels
Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins)
can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a
voltage, bus, bandwidth level, and a DVM value.
- qcom,gpu-pwrlevel-bins: Contains one or more qcom,gpu-pwrlevels sets
Properties:
- compatible: Must be qcom,gpu-pwrlevel-bins
- qcom,gpu-pwrlevels: Defines a set of powerlevels
Properties:
- qcom,speed-bin: Speed bin identifier for the set - must match
the value read from the hardware
- qcom,initial-pwrlevel: GPU wakeup powerlevel
- qcom,gpu-pwrlevel: A single powerlevel
- qcom,ca-target-pwrlevel:
This value indicates which qcom,gpu-pwrlevel
to jump on in case of context aware power level
jump.
Properties:
- reg: Index of the powerlevel (0 = highest perf)
- qcom,gpu-freq GPU frequency for the powerlevel (in Hz)
- qcom,bus-freq Index to a bus level (defined by the bus
settings)
- qcom,bus-min Minimum bus level to set for the power level
- qcom,bus-max maximum bus level to set for the power level
- qcom,dvm-val: Value that is used as a register setting for
the ACD power feature. It helps determine the
threshold for when ACD activates. 0xFFFFFFFF
is the default value, and the setting where
ACD will never activate.