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Russ Anderson 2022c1f136 [IA64] Update Altix nofault code ... Montecito and Montvale behaves slightly differently than previous Itanium processors, resulting in the MCA due to a failed PIO read to sometimes surfacing outside the nofault code. This code is based on discussions with Intel CPU architects and verified at customer sites. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>		17 years ago
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sn2	ia64: fix sn to add include files using EXTRA_CFLAGS	18 years ago
Makefile	ia64: fix sn to add include files using EXTRA_CFLAGS	18 years ago
bte.c	[IA64] Fix Altix BTE error return status	17 years ago
bte_error.c	[IA64] Fix Altix BTE error return status	17 years ago
huberror.c	…
idle.c	…
io_acpi_init.c	…
io_common.c	[IA64] Add missing "space" to concatenated strings	17 years ago
io_init.c	…
iomv.c	…
irq.c	[IA64] Disable/re-enable CPE interrupts on Altix	18 years ago
klconflib.c	…
machvec.c	…
mca.c	[IA64] arch/ia64/sn/kernel/mca.c: undo lock when sn_oemdata can't be extended	18 years ago
msi_sn.c	…
pio_phys.S	…
setup.c	…
tiocx.c	Driver core: change add_uevent_var to use a struct	18 years ago
xp_main.c	…
xp_nofault.S	[IA64] Update Altix nofault code	17 years ago
xpc_channel.c	…
xpc_main.c	[IA64] XPC heartbeat timer function must run on CPU 0	17 years ago
xpc_partition.c	…
xpnet.c	Add missing newlines to some uses of dev_<level> messages	18 years ago