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812 lines
20 KiB
812 lines
20 KiB
/*
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-------------------------------------------------------------------------
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i2c-algo-ite.c i2c driver algorithms for ITE adapters
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Hai-Pao Fan, MontaVista Software, Inc.
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hpfan@mvista.com or source@mvista.com
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Copyright 2000 MontaVista Software Inc.
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---------------------------------------------------------------------------
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This file was highly leveraged from i2c-algo-pcf.c, which was created
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by Simon G. Vogl and Hans Berglund:
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Copyright (C) 1995-1997 Simon G. Vogl
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1998-2000 Hans Berglund
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* ------------------------------------------------------------------------- */
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/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and
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Frodo Looijaard <frodol@dds.nl> ,and also from Martin Bailey
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<mbailey@littlefeet-inc.com> */
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <asm/uaccess.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-ite.h>
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#include "i2c-algo-ite.h"
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#define PM_DSR IT8172_PCI_IO_BASE + IT_PM_DSR
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#define PM_IBSR IT8172_PCI_IO_BASE + IT_PM_DSR + 0x04
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#define GPIO_CCR IT8172_PCI_IO_BASE + IT_GPCCR
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#define DEB2(x) if (i2c_debug>=2) x
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#define DEB3(x) if (i2c_debug>=3) x /* print several statistical values*/
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#define DEF_TIMEOUT 16
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/* module parameters:
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*/
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static int i2c_debug;
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static int iic_test; /* see if the line-setting functions work */
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/* --- setting states on the bus with the right timing: --------------- */
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#define get_clock(adap) adap->getclock(adap->data)
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#define iic_outw(adap, reg, val) adap->setiic(adap->data, reg, val)
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#define iic_inw(adap, reg) adap->getiic(adap->data, reg)
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/* --- other auxiliary functions -------------------------------------- */
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static void iic_start(struct i2c_algo_iic_data *adap)
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{
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iic_outw(adap,ITE_I2CHCR,ITE_CMD);
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}
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static void iic_stop(struct i2c_algo_iic_data *adap)
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{
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iic_outw(adap,ITE_I2CHCR,0);
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iic_outw(adap,ITE_I2CHSR,ITE_I2CHSR_TDI);
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}
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static void iic_reset(struct i2c_algo_iic_data *adap)
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{
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iic_outw(adap, PM_IBSR, iic_inw(adap, PM_IBSR) | 0x80);
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}
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static int wait_for_bb(struct i2c_algo_iic_data *adap)
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{
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int timeout = DEF_TIMEOUT;
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short status;
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status = iic_inw(adap, ITE_I2CHSR);
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#ifndef STUB_I2C
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while (timeout-- && (status & ITE_I2CHSR_HB)) {
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udelay(1000); /* How much is this? */
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status = iic_inw(adap, ITE_I2CHSR);
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}
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#endif
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if (timeout<=0) {
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printk(KERN_ERR "Timeout, host is busy\n");
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iic_reset(adap);
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}
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return(timeout<=0);
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}
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/* After we issue a transaction on the IIC bus, this function
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* is called. It puts this process to sleep until we get an interrupt from
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* from the controller telling us that the transaction we requested in complete.
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*/
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static int wait_for_pin(struct i2c_algo_iic_data *adap, short *status) {
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int timeout = DEF_TIMEOUT;
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timeout = wait_for_bb(adap);
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if (timeout) {
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DEB2(printk("Timeout waiting for host not busy\n");)
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return -EIO;
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}
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timeout = DEF_TIMEOUT;
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*status = iic_inw(adap, ITE_I2CHSR);
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#ifndef STUB_I2C
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while (timeout-- && !(*status & ITE_I2CHSR_TDI)) {
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adap->waitforpin();
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*status = iic_inw(adap, ITE_I2CHSR);
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}
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#endif
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if (timeout <= 0)
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return(-1);
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else
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return(0);
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}
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static int wait_for_fe(struct i2c_algo_iic_data *adap, short *status)
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{
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int timeout = DEF_TIMEOUT;
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*status = iic_inw(adap, ITE_I2CFSR);
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#ifndef STUB_I2C
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while (timeout-- && (*status & ITE_I2CFSR_FE)) {
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udelay(1000);
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iic_inw(adap, ITE_I2CFSR);
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}
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#endif
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if (timeout <= 0)
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return(-1);
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else
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return(0);
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}
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static int iic_init (struct i2c_algo_iic_data *adap)
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{
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short i;
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/* Clear bit 7 to set I2C to normal operation mode */
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i=iic_inw(adap, PM_DSR)& 0xff7f;
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iic_outw(adap, PM_DSR, i);
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/* set IT_GPCCR port C bit 2&3 as function 2 */
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i = iic_inw(adap, GPIO_CCR) & 0xfc0f;
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iic_outw(adap,GPIO_CCR,i);
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/* Clear slave address/sub-address */
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iic_outw(adap,ITE_I2CSAR, 0);
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iic_outw(adap,ITE_I2CSSAR, 0);
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/* Set clock counter register */
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iic_outw(adap,ITE_I2CCKCNT, get_clock(adap));
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/* Set START/reSTART/STOP time registers */
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iic_outw(adap,ITE_I2CSHDR, 0x0a);
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iic_outw(adap,ITE_I2CRSUR, 0x0a);
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iic_outw(adap,ITE_I2CPSUR, 0x0a);
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/* Enable interrupts on completing the current transaction */
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iic_outw(adap,ITE_I2CHCR, ITE_I2CHCR_IE | ITE_I2CHCR_HCE);
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/* Clear transfer count */
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iic_outw(adap,ITE_I2CFBCR, 0x0);
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DEB2(printk("iic_init: Initialized IIC on ITE 0x%x\n",
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iic_inw(adap, ITE_I2CHSR)));
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return 0;
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}
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/*
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* Sanity check for the adapter hardware - check the reaction of
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* the bus lines only if it seems to be idle.
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*/
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static int test_bus(struct i2c_algo_iic_data *adap, char *name) {
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#if 0
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int scl,sda;
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sda=getsda(adap);
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if (adap->getscl==NULL) {
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printk("test_bus: Warning: Adapter can't read from clock line - skipping test.\n");
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return 0;
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}
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scl=getscl(adap);
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printk("test_bus: Adapter: %s scl: %d sda: %d -- testing...\n",
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name,getscl(adap),getsda(adap));
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if (!scl || !sda ) {
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printk("test_bus: %s seems to be busy.\n",adap->name);
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goto bailout;
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}
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sdalo(adap);
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printk("test_bus:1 scl: %d sda: %d \n",getscl(adap),
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getsda(adap));
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if ( 0 != getsda(adap) ) {
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printk("test_bus: %s SDA stuck high!\n",name);
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sdahi(adap);
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goto bailout;
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}
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if ( 0 == getscl(adap) ) {
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printk("test_bus: %s SCL unexpected low while pulling SDA low!\n",
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name);
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goto bailout;
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}
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sdahi(adap);
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printk("test_bus:2 scl: %d sda: %d \n",getscl(adap),
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getsda(adap));
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if ( 0 == getsda(adap) ) {
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printk("test_bus: %s SDA stuck low!\n",name);
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sdahi(adap);
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goto bailout;
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}
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if ( 0 == getscl(adap) ) {
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printk("test_bus: %s SCL unexpected low while SDA high!\n",
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adap->name);
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goto bailout;
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}
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scllo(adap);
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printk("test_bus:3 scl: %d sda: %d \n",getscl(adap),
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getsda(adap));
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if ( 0 != getscl(adap) ) {
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sclhi(adap);
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goto bailout;
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}
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if ( 0 == getsda(adap) ) {
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printk("test_bus: %s SDA unexpected low while pulling SCL low!\n",
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name);
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goto bailout;
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}
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sclhi(adap);
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printk("test_bus:4 scl: %d sda: %d \n",getscl(adap),
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getsda(adap));
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if ( 0 == getscl(adap) ) {
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printk("test_bus: %s SCL stuck low!\n",name);
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sclhi(adap);
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goto bailout;
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}
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if ( 0 == getsda(adap) ) {
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printk("test_bus: %s SDA unexpected low while SCL high!\n",
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name);
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goto bailout;
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}
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printk("test_bus: %s passed test.\n",name);
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return 0;
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bailout:
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sdahi(adap);
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sclhi(adap);
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return -ENODEV;
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#endif
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return (0);
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}
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/* ----- Utility functions
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*/
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/* Verify the device we want to talk to on the IIC bus really exists. */
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static inline int try_address(struct i2c_algo_iic_data *adap,
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unsigned int addr, int retries)
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{
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int i, ret = -1;
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short status;
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for (i=0;i<retries;i++) {
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iic_outw(adap, ITE_I2CSAR, addr);
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iic_start(adap);
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if (wait_for_pin(adap, &status) == 0) {
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if ((status & ITE_I2CHSR_DNE) == 0) {
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iic_stop(adap);
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iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
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ret=1;
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break; /* success! */
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}
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}
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iic_stop(adap);
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udelay(adap->udelay);
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}
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DEB2(if (i) printk("try_address: needed %d retries for 0x%x\n",i,
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addr));
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return ret;
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}
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static int iic_sendbytes(struct i2c_adapter *i2c_adap,const char *buf,
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int count)
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{
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struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
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int wrcount=0, timeout;
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short status;
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int loops, remainder, i, j;
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union {
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char byte[2];
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unsigned short word;
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} tmp;
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iic_outw(adap, ITE_I2CSSAR, (unsigned short)buf[wrcount++]);
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count--;
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if (count == 0)
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return -EIO;
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loops = count / 32; /* 32-byte FIFO */
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remainder = count % 32;
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if(loops) {
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for(i=0; i<loops; i++) {
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iic_outw(adap, ITE_I2CFBCR, 32);
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for(j=0; j<32/2; j++) {
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tmp.byte[1] = buf[wrcount++];
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tmp.byte[0] = buf[wrcount++];
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iic_outw(adap, ITE_I2CFDR, tmp.word);
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}
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/* status FIFO overrun */
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iic_inw(adap, ITE_I2CFSR);
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iic_inw(adap, ITE_I2CFBCR);
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iic_outw(adap, ITE_I2CHCR, ITE_WRITE); /* Issue WRITE command */
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/* Wait for transmission to complete */
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timeout = wait_for_pin(adap, &status);
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if(timeout) {
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iic_stop(adap);
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printk("iic_sendbytes: %s write timeout.\n", i2c_adap->name);
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return -EREMOTEIO; /* got a better one ?? */
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}
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if (status & ITE_I2CHSR_DB) {
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iic_stop(adap);
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printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name);
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return -EREMOTEIO; /* got a better one ?? */
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}
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}
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}
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if(remainder) {
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iic_outw(adap, ITE_I2CFBCR, remainder);
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for(i=0; i<remainder/2; i++) {
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tmp.byte[1] = buf[wrcount++];
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tmp.byte[0] = buf[wrcount++];
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iic_outw(adap, ITE_I2CFDR, tmp.word);
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}
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/* status FIFO overrun */
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iic_inw(adap, ITE_I2CFSR);
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iic_inw(adap, ITE_I2CFBCR);
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iic_outw(adap, ITE_I2CHCR, ITE_WRITE); /* Issue WRITE command */
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timeout = wait_for_pin(adap, &status);
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if(timeout) {
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iic_stop(adap);
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printk("iic_sendbytes: %s write timeout.\n", i2c_adap->name);
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return -EREMOTEIO; /* got a better one ?? */
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}
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#ifndef STUB_I2C
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if (status & ITE_I2CHSR_DB) {
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iic_stop(adap);
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printk("iic_sendbytes: %s write error - no ack.\n", i2c_adap->name);
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return -EREMOTEIO; /* got a better one ?? */
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}
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#endif
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}
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iic_stop(adap);
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return wrcount;
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}
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static int iic_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count,
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int sread)
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{
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int rdcount=0, i, timeout;
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short status;
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struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
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int loops, remainder, j;
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union {
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char byte[2];
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unsigned short word;
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} tmp;
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loops = count / 32; /* 32-byte FIFO */
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remainder = count % 32;
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if(loops) {
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for(i=0; i<loops; i++) {
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iic_outw(adap, ITE_I2CFBCR, 32);
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if (sread)
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iic_outw(adap, ITE_I2CHCR, ITE_SREAD);
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else
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iic_outw(adap, ITE_I2CHCR, ITE_READ); /* Issue READ command */
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timeout = wait_for_pin(adap, &status);
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if(timeout) {
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iic_stop(adap);
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printk("iic_readbytes: %s read timeout.\n", i2c_adap->name);
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return (-1);
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}
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#ifndef STUB_I2C
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if (status & ITE_I2CHSR_DB) {
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iic_stop(adap);
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printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name);
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return (-1);
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}
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#endif
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timeout = wait_for_fe(adap, &status);
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if(timeout) {
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iic_stop(adap);
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printk("iic_readbytes: %s FIFO is empty\n", i2c_adap->name);
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return (-1);
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}
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for(j=0; j<32/2; j++) {
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tmp.word = iic_inw(adap, ITE_I2CFDR);
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buf[rdcount++] = tmp.byte[1];
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buf[rdcount++] = tmp.byte[0];
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}
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/* status FIFO underrun */
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iic_inw(adap, ITE_I2CFSR);
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}
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}
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if(remainder) {
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remainder=(remainder+1)/2 * 2;
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iic_outw(adap, ITE_I2CFBCR, remainder);
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if (sread)
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iic_outw(adap, ITE_I2CHCR, ITE_SREAD);
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else
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iic_outw(adap, ITE_I2CHCR, ITE_READ); /* Issue READ command */
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timeout = wait_for_pin(adap, &status);
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if(timeout) {
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iic_stop(adap);
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printk("iic_readbytes: %s read timeout.\n", i2c_adap->name);
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return (-1);
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}
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#ifndef STUB_I2C
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if (status & ITE_I2CHSR_DB) {
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iic_stop(adap);
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printk("iic_readbytes: %s read error - no ack.\n", i2c_adap->name);
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return (-1);
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}
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#endif
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timeout = wait_for_fe(adap, &status);
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if(timeout) {
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iic_stop(adap);
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printk("iic_readbytes: %s FIFO is empty\n", i2c_adap->name);
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return (-1);
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}
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for(i=0; i<(remainder+1)/2; i++) {
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tmp.word = iic_inw(adap, ITE_I2CFDR);
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buf[rdcount++] = tmp.byte[1];
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buf[rdcount++] = tmp.byte[0];
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}
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/* status FIFO underrun */
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iic_inw(adap, ITE_I2CFSR);
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}
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iic_stop(adap);
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return rdcount;
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}
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/* This function implements combined transactions. Combined
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|
* transactions consist of combinations of reading and writing blocks of data.
|
|
* Each transfer (i.e. a read or a write) is separated by a repeated start
|
|
* condition.
|
|
*/
|
|
#if 0
|
|
static int iic_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
|
|
{
|
|
int i;
|
|
struct i2c_msg *pmsg;
|
|
int ret;
|
|
|
|
DEB2(printk("Beginning combined transaction\n"));
|
|
|
|
for(i=0; i<(num-1); i++) {
|
|
pmsg = &msgs[i];
|
|
if(pmsg->flags & I2C_M_RD) {
|
|
DEB2(printk(" This one is a read\n"));
|
|
ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER);
|
|
}
|
|
else if(!(pmsg->flags & I2C_M_RD)) {
|
|
DEB2(printk("This one is a write\n"));
|
|
ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_COMBINED_XFER);
|
|
}
|
|
}
|
|
/* Last read or write segment needs to be terminated with a stop */
|
|
pmsg = &msgs[i];
|
|
|
|
if(pmsg->flags & I2C_M_RD) {
|
|
DEB2(printk("Doing the last read\n"));
|
|
ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
|
|
}
|
|
else if(!(pmsg->flags & I2C_M_RD)) {
|
|
DEB2(printk("Doing the last write\n"));
|
|
ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
|
|
/* Whenever we initiate a transaction, the first byte clocked
|
|
* onto the bus after the start condition is the address (7 bit) of the
|
|
* device we want to talk to. This function manipulates the address specified
|
|
* so that it makes sense to the hardware when written to the IIC peripheral.
|
|
*
|
|
* Note: 10 bit addresses are not supported in this driver, although they are
|
|
* supported by the hardware. This functionality needs to be implemented.
|
|
*/
|
|
static inline int iic_doAddress(struct i2c_algo_iic_data *adap,
|
|
struct i2c_msg *msg, int retries)
|
|
{
|
|
unsigned short flags = msg->flags;
|
|
unsigned int addr;
|
|
int ret;
|
|
|
|
/* Ten bit addresses not supported right now */
|
|
if ( (flags & I2C_M_TEN) ) {
|
|
#if 0
|
|
addr = 0xf0 | (( msg->addr >> 7) & 0x03);
|
|
DEB2(printk("addr0: %d\n",addr));
|
|
ret = try_address(adap, addr, retries);
|
|
if (ret!=1) {
|
|
printk("iic_doAddress: died at extended address code.\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
iic_outw(adap,msg->addr & 0x7f);
|
|
if (ret != 1) {
|
|
printk("iic_doAddress: died at 2nd address code.\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
if ( flags & I2C_M_RD ) {
|
|
i2c_repstart(adap);
|
|
addr |= 0x01;
|
|
ret = try_address(adap, addr, retries);
|
|
if (ret!=1) {
|
|
printk("iic_doAddress: died at extended address code.\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
#endif
|
|
} else {
|
|
|
|
addr = ( msg->addr << 1 );
|
|
|
|
#if 0
|
|
if (flags & I2C_M_RD )
|
|
addr |= 1;
|
|
if (flags & I2C_M_REV_DIR_ADDR )
|
|
addr ^= 1;
|
|
#endif
|
|
|
|
if (iic_inw(adap, ITE_I2CSAR) != addr) {
|
|
iic_outw(adap, ITE_I2CSAR, addr);
|
|
ret = try_address(adap, addr, retries);
|
|
if (ret!=1) {
|
|
printk("iic_doAddress: died at address code.\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* Description: Prepares the controller for a transaction (clearing status
|
|
* registers, data buffers, etc), and then calls either iic_readbytes or
|
|
* iic_sendbytes to do the actual transaction.
|
|
*
|
|
* still to be done: Before we issue a transaction, we should
|
|
* verify that the bus is not busy or in some unknown state.
|
|
*/
|
|
static int iic_xfer(struct i2c_adapter *i2c_adap,
|
|
struct i2c_msg *msgs,
|
|
int num)
|
|
{
|
|
struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
|
|
struct i2c_msg *pmsg;
|
|
int i = 0;
|
|
int ret, timeout;
|
|
|
|
pmsg = &msgs[i];
|
|
|
|
if(!pmsg->len) {
|
|
DEB2(printk("iic_xfer: read/write length is 0\n");)
|
|
return -EIO;
|
|
}
|
|
if(!(pmsg->flags & I2C_M_RD) && (!(pmsg->len)%2) ) {
|
|
DEB2(printk("iic_xfer: write buffer length is not odd\n");)
|
|
return -EIO;
|
|
}
|
|
|
|
/* Wait for any pending transfers to complete */
|
|
timeout = wait_for_bb(adap);
|
|
if (timeout) {
|
|
DEB2(printk("iic_xfer: Timeout waiting for host not busy\n");)
|
|
return -EIO;
|
|
}
|
|
|
|
/* Flush FIFO */
|
|
iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
|
|
|
|
/* Load address */
|
|
ret = iic_doAddress(adap, pmsg, i2c_adap->retries);
|
|
if (ret)
|
|
return -EIO;
|
|
|
|
#if 0
|
|
/* Combined transaction (read and write) */
|
|
if(num > 1) {
|
|
DEB2(printk("iic_xfer: Call combined transaction\n"));
|
|
ret = iic_combined_transaction(i2c_adap, msgs, num);
|
|
}
|
|
#endif
|
|
|
|
DEB3(printk("iic_xfer: Msg %d, addr=0x%x, flags=0x%x, len=%d\n",
|
|
i, msgs[i].addr, msgs[i].flags, msgs[i].len);)
|
|
|
|
if(pmsg->flags & I2C_M_RD) /* Read */
|
|
ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, 0);
|
|
else { /* Write */
|
|
udelay(1000);
|
|
ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len);
|
|
}
|
|
|
|
if (ret != pmsg->len)
|
|
DEB3(printk("iic_xfer: error or fail on read/write %d bytes.\n",ret));
|
|
else
|
|
DEB3(printk("iic_xfer: read/write %d bytes.\n",ret));
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
/* Implements device specific ioctls. Higher level ioctls can
|
|
* be found in i2c-core.c and are typical of any i2c controller (specifying
|
|
* slave address, timeouts, etc). These ioctls take advantage of any hardware
|
|
* features built into the controller for which this algorithm-adapter set
|
|
* was written. These ioctls allow you to take control of the data and clock
|
|
* lines and set the either high or low,
|
|
* similar to a GPIO pin.
|
|
*/
|
|
static int algo_control(struct i2c_adapter *adapter,
|
|
unsigned int cmd, unsigned long arg)
|
|
{
|
|
|
|
struct i2c_algo_iic_data *adap = adapter->algo_data;
|
|
struct i2c_iic_msg s_msg;
|
|
char *buf;
|
|
int ret;
|
|
|
|
if (cmd == I2C_SREAD) {
|
|
if(copy_from_user(&s_msg, (struct i2c_iic_msg *)arg,
|
|
sizeof(struct i2c_iic_msg)))
|
|
return -EFAULT;
|
|
buf = kmalloc(s_msg.len, GFP_KERNEL);
|
|
if (buf== NULL)
|
|
return -ENOMEM;
|
|
|
|
/* Flush FIFO */
|
|
iic_outw(adap, ITE_I2CFCR, ITE_I2CFCR_FLUSH);
|
|
|
|
/* Load address */
|
|
iic_outw(adap, ITE_I2CSAR,s_msg.addr<<1);
|
|
iic_outw(adap, ITE_I2CSSAR,s_msg.waddr & 0xff);
|
|
|
|
ret = iic_readbytes(adapter, buf, s_msg.len, 1);
|
|
if (ret>=0) {
|
|
if(copy_to_user( s_msg.buf, buf, s_msg.len) )
|
|
ret = -EFAULT;
|
|
}
|
|
kfree(buf);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
static u32 iic_func(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
|
|
I2C_FUNC_PROTOCOL_MANGLING;
|
|
}
|
|
|
|
/* -----exported algorithm data: ------------------------------------- */
|
|
|
|
static struct i2c_algorithm iic_algo = {
|
|
.name = "ITE IIC algorithm",
|
|
.id = I2C_ALGO_IIC,
|
|
.master_xfer = iic_xfer,
|
|
.algo_control = algo_control, /* ioctl */
|
|
.functionality = iic_func,
|
|
};
|
|
|
|
|
|
/*
|
|
* registering functions to load algorithms at runtime
|
|
*/
|
|
int i2c_iic_add_bus(struct i2c_adapter *adap)
|
|
{
|
|
struct i2c_algo_iic_data *iic_adap = adap->algo_data;
|
|
|
|
if (iic_test) {
|
|
int ret = test_bus(iic_adap, adap->name);
|
|
if (ret<0)
|
|
return -ENODEV;
|
|
}
|
|
|
|
DEB2(printk("i2c-algo-ite: hw routines for %s registered.\n",
|
|
adap->name));
|
|
|
|
/* register new adapter to i2c module... */
|
|
|
|
adap->id |= iic_algo.id;
|
|
adap->algo = &iic_algo;
|
|
|
|
adap->timeout = 100; /* default values, should */
|
|
adap->retries = 3; /* be replaced by defines */
|
|
adap->flags = 0;
|
|
|
|
i2c_add_adapter(adap);
|
|
iic_init(iic_adap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
int i2c_iic_del_bus(struct i2c_adapter *adap)
|
|
{
|
|
int res;
|
|
if ((res = i2c_del_adapter(adap)) < 0)
|
|
return res;
|
|
DEB2(printk("i2c-algo-ite: adapter unregistered: %s\n",adap->name));
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
int __init i2c_algo_iic_init (void)
|
|
{
|
|
printk(KERN_INFO "ITE iic (i2c) algorithm module\n");
|
|
return 0;
|
|
}
|
|
|
|
|
|
void i2c_algo_iic_exit(void)
|
|
{
|
|
return;
|
|
}
|
|
|
|
|
|
EXPORT_SYMBOL(i2c_iic_add_bus);
|
|
EXPORT_SYMBOL(i2c_iic_del_bus);
|
|
|
|
/* The MODULE_* macros resolve to nothing if MODULES is not defined
|
|
* when this file is compiled.
|
|
*/
|
|
MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
|
|
MODULE_DESCRIPTION("ITE iic algorithm");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
module_param(iic_test, bool, 0);
|
|
module_param(i2c_debug, int, S_IRUGO | S_IWUSR);
|
|
|
|
MODULE_PARM_DESC(iic_test, "Test if the I2C bus is available");
|
|
MODULE_PARM_DESC(i2c_debug,
|
|
"debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol");
|
|
|
|
|
|
/* This function resolves to init_module (the function invoked when a module
|
|
* is loaded via insmod) when this file is compiled with MODULES defined.
|
|
* Otherwise (i.e. if you want this driver statically linked to the kernel),
|
|
* a pointer to this function is stored in a table and called
|
|
* during the initialization of the kernel (in do_basic_setup in /init/main.c)
|
|
*
|
|
* All this functionality is complements of the macros defined in linux/init.h
|
|
*/
|
|
module_init(i2c_algo_iic_init);
|
|
|
|
|
|
/* If MODULES is defined when this file is compiled, then this function will
|
|
* resolved to cleanup_module.
|
|
*/
|
|
module_exit(i2c_algo_iic_exit);
|
|
|