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417 lines
11 KiB
417 lines
11 KiB
/*
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* Low-Level PCI Support for the SH7751
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*
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* Dustin McIntire (dustin@sensoria.com)
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* Derived from arch/i386/kernel/pci-*.c which bore the message:
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* (c) 1999--2000 Martin Mares <mj@ucw.cz>
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*
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* Ported to the new API by Paul Mundt <lethal@linux-sh.org>
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* With cleanup by Paul van Gool <pvangool@mimotech.com>
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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*/
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#undef DEBUG
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <asm/machvec.h>
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#include <asm/io.h>
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#include "pci-sh7751.h"
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static unsigned int pci_probe = PCI_PROBE_CONF1;
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extern int pci_fixup_pcic(void);
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void pcibios_fixup_irqs(void) __attribute__ ((weak));
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/*
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* Direct access to PCI hardware...
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*/
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#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
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/*
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* Functions for accessing PCI configuration space with type 1 accesses
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*/
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static int sh7751_pci_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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unsigned long flags;
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u32 data;
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/*
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* PCIPDR may only be accessed as 32 bit words,
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* so we must do byte alignment by hand
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*/
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local_irq_save(flags);
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outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR));
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data = inl(PCI_REG(SH7751_PCIPDR));
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local_irq_restore(flags);
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switch (size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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*val = (data >> ((where & 2) << 3)) & 0xffff;
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break;
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case 4:
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*val = data;
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break;
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* Since SH7751 only does 32bit access we'll have to do a read,
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* mask,write operation.
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* We'll allow an odd byte offset, though it should be illegal.
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*/
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static int sh7751_pci_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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unsigned long flags;
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int shift;
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u32 data;
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local_irq_save(flags);
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outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR));
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data = inl(PCI_REG(SH7751_PCIPDR));
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local_irq_restore(flags);
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switch (size) {
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case 1:
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shift = (where & 3) << 3;
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data &= ~(0xff << shift);
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data |= ((val & 0xff) << shift);
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break;
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case 2:
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shift = (where & 2) << 3;
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data &= ~(0xffff << shift);
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data |= ((val & 0xffff) << shift);
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break;
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case 4:
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data = val;
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break;
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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outl(data, PCI_REG(SH7751_PCIPDR));
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return PCIBIOS_SUCCESSFUL;
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}
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#undef CONFIG_CMD
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struct pci_ops sh7751_pci_ops = {
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.read = sh7751_pci_read,
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.write = sh7751_pci_write,
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};
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static int __init pci_check_direct(void)
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{
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unsigned int tmp, id;
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/* check for SH7751/SH7751R hardware */
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id = inl(SH7751_PCIREG_BASE+SH7751_PCICONF0);
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if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
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id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
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pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
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return -ENODEV;
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}
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/*
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* Check if configuration works.
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*/
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if (pci_probe & PCI_PROBE_CONF1) {
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tmp = inl (PCI_REG(SH7751_PCIPAR));
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outl (0x80000000, PCI_REG(SH7751_PCIPAR));
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if (inl (PCI_REG(SH7751_PCIPAR)) == 0x80000000) {
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outl (tmp, PCI_REG(SH7751_PCIPAR));
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printk(KERN_INFO "PCI: Using configuration type 1\n");
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request_region(PCI_REG(SH7751_PCIPAR), 8, "PCI conf1");
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return 0;
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}
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outl (tmp, PCI_REG(SH7751_PCIPAR));
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}
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pr_debug("PCI: pci_check_direct failed\n");
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return -EINVAL;
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}
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/***************************************************************************************/
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/*
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* Handle bus scanning and fixups ....
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*/
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static void __init pci_fixup_ide_bases(struct pci_dev *d)
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{
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int i;
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
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*/
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if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d));
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for(i=0; i<4; i++) {
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struct resource *r = &d->resource[i];
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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/*
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* Called after each bus is probed, but before its children
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* are examined.
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*/
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void __init pcibios_fixup_bus(struct pci_bus *b)
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{
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pci_read_bridge_bases(b);
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}
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/*
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* Initialization. Try all known PCI access methods. Note that we support
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* using both PCI BIOS and direct access: in such cases, we use I/O ports
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* to access config space.
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*
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* Note that the platform specific initialization (BSC registers, and memory
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* space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it
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* exitst and via the platform defined function pcibios_init_platform().
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* See pci_bigsur.c for implementation;
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*
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* The BIOS version of the pci functions is not yet implemented but it is left
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* in for completeness. Currently an error will be genereated at compile time.
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*/
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static int __init sh7751_pci_init(void)
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{
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int ret;
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pr_debug("PCI: Starting intialization.\n");
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if ((ret = pci_check_direct()) != 0)
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return ret;
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return pcibios_init_platform();
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}
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subsys_initcall(sh7751_pci_init);
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static int __init __area_sdram_check(unsigned int area)
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{
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u32 word;
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word = inl(SH7751_BCR1);
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/* check BCR for SDRAM in area */
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if(((word >> area) & 1) == 0) {
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printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
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area, word);
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return 0;
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}
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outl(word, PCI_REG(SH7751_PCIBCR1));
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word = (u16)inw(SH7751_BCR2);
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/* check BCR2 for 32bit SDRAM interface*/
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if(((word >> (area << 1)) & 0x3) != 0x3) {
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printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
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area, word);
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return 0;
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}
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outl(word, PCI_REG(SH7751_PCIBCR2));
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return 1;
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}
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int __init sh7751_pcic_init(struct sh7751_pci_address_map *map)
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{
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u32 reg;
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u32 word;
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/* Set the BCR's to enable PCI access */
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reg = inl(SH7751_BCR1);
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reg |= 0x80000;
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outl(reg, SH7751_BCR1);
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/* Turn the clocks back on (not done in reset)*/
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outl(0, PCI_REG(SH7751_PCICLKR));
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/* Clear Powerdown IRQ's (not done in reset) */
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word = SH7751_PCIPINT_D3 | SH7751_PCIPINT_D0;
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outl(word, PCI_REG(SH7751_PCIPINT));
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/*
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* This code is unused for some boards as it is done in the
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* bootloader and doing it here means the MAC addresses loaded
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* by the bootloader get lost.
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*/
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if (!(map->flags & SH7751_PCIC_NO_RESET)) {
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/* toggle PCI reset pin */
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word = SH7751_PCICR_PREFIX | SH7751_PCICR_PRST;
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outl(word,PCI_REG(SH7751_PCICR));
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/* Wait for a long time... not 1 sec. but long enough */
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mdelay(100);
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word = SH7751_PCICR_PREFIX;
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outl(word,PCI_REG(SH7751_PCICR));
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}
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/* set the command/status bits to:
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* Wait Cycle Control + Parity Enable + Bus Master +
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* Mem space enable
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*/
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word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
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SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
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outl(word, PCI_REG(SH7751_PCICONF1));
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/* define this host as the host bridge */
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word = SH7751_PCI_HOST_BRIDGE << 24;
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outl(word, PCI_REG(SH7751_PCICONF2));
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/* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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* Window0 = map->window0.size @ non-cached area base = SDRAM
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* Window1 = map->window1.size @ cached area base = SDRAM
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*/
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word = map->window0.size - 1;
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outl(word, PCI_REG(SH7751_PCILSR0));
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word = map->window1.size - 1;
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outl(word, PCI_REG(SH7751_PCILSR1));
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/* Set the values on window 0 PCI config registers */
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word = P2SEGADDR(map->window0.base);
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outl(word, PCI_REG(SH7751_PCILAR0));
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outl(word, PCI_REG(SH7751_PCICONF5));
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/* Set the values on window 1 PCI config registers */
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word = PHYSADDR(map->window1.base);
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outl(word, PCI_REG(SH7751_PCILAR1));
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outl(word, PCI_REG(SH7751_PCICONF6));
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/* Set the local 16MB PCI memory space window to
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* the lowest PCI mapped address
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*/
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word = PCIBIOS_MIN_MEM & SH7751_PCIMBR_MASK;
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PCIDBG(2,"PCI: Setting upper bits of Memory window to 0x%x\n", word);
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outl(word , PCI_REG(SH7751_PCIMBR));
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/* Map IO space into PCI IO window
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* The IO window is 64K-PCIBIOS_MIN_IO in size
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* IO addresses will be translated to the
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* PCI IO window base address
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*/
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PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
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(64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO);
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/*
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* XXX: For now, leave this board-specific. In the event we have other
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* boards that need to do similar work, this can be wrapped.
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*/
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#ifdef CONFIG_SH_BIGSUR
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bigsur_port_map(PCIBIOS_MIN_IO, (64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO,0);
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#endif
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/* Make sure the MSB's of IO window are set to access PCI space correctly */
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word = PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK;
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PCIDBG(2,"PCI: Setting upper bits of IO window to 0x%x\n", word);
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outl(word, PCI_REG(SH7751_PCIIOBR));
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/* Set PCI WCRx, BCRx's, copy from BSC locations */
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/* check BCR for SDRAM in specified area */
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switch (map->window0.base) {
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case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break;
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case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break;
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case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break;
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case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break;
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case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break;
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case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break;
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case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break;
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}
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if (!word)
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return 0;
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/* configure the wait control registers */
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word = inl(SH7751_WCR1);
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outl(word, PCI_REG(SH7751_PCIWCR1));
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word = inl(SH7751_WCR2);
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outl(word, PCI_REG(SH7751_PCIWCR2));
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word = inl(SH7751_WCR3);
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outl(word, PCI_REG(SH7751_PCIWCR3));
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word = inl(SH7751_MCR);
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outl(word, PCI_REG(SH7751_PCIMCR));
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/* NOTE: I'm ignoring the PCI error IRQs for now..
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* TODO: add support for the internal error interrupts and
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* DMA interrupts...
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*/
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#ifdef CONFIG_SH_RTS7751R2D
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pci_fixup_pcic();
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#endif
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/* SH7751 init done, set central function init complete */
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/* use round robin mode to stop a device starving/overruning */
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word = SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN | SH7751_PCICR_ARBM;
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outl(word,PCI_REG(SH7751_PCICR));
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return 1;
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}
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char * __init pcibios_setup(char *str)
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{
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if (!strcmp(str, "off")) {
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pci_probe = 0;
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return NULL;
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}
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return str;
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}
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/*
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* IRQ functions
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*/
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static u8 __init sh7751_no_swizzle(struct pci_dev *dev, u8 *pin)
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{
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/* no swizzling */
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return PCI_SLOT(dev->devfn);
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}
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static int sh7751_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq = -1;
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/* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
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irq = pcibios_map_platform_irq(slot,pin);
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if( irq < 0 ) {
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pr_debug("PCI: Error mapping IRQ on device %s\n", pci_name(dev));
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return irq;
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}
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pr_debug("Setting IRQ for slot %s to %d\n", pci_name(dev), irq);
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return irq;
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}
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void __init pcibios_fixup_irqs(void)
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{
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pci_fixup_irqs(sh7751_no_swizzle, sh7751_pci_lookup_irq);
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}
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