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87 lines
2.1 KiB
87 lines
2.1 KiB
/*
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* Blackfin On-Chip SPI Driver
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _SPI_CHANNEL_H_
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#define _SPI_CHANNEL_H_
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#define MIN_SPI_BAUD_VAL 2
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#define BIT_CTL_ENABLE 0x4000
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#define BIT_CTL_OPENDRAIN 0x2000
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#define BIT_CTL_MASTER 0x1000
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#define BIT_CTL_CPOL 0x0800
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#define BIT_CTL_CPHA 0x0400
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#define BIT_CTL_LSBF 0x0200
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#define BIT_CTL_WORDSIZE 0x0100
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#define BIT_CTL_EMISO 0x0020
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#define BIT_CTL_PSSE 0x0010
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#define BIT_CTL_GM 0x0008
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#define BIT_CTL_SZ 0x0004
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#define BIT_CTL_RXMOD 0x0000
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#define BIT_CTL_TXMOD 0x0001
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#define BIT_CTL_TIMOD_DMA_TX 0x0003
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#define BIT_CTL_TIMOD_DMA_RX 0x0002
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#define BIT_CTL_SENDOPT 0x0004
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#define BIT_CTL_TIMOD 0x0003
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#define BIT_STAT_SPIF 0x0001
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#define BIT_STAT_MODF 0x0002
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#define BIT_STAT_TXE 0x0004
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#define BIT_STAT_TXS 0x0008
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#define BIT_STAT_RBSY 0x0010
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#define BIT_STAT_RXS 0x0020
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#define BIT_STAT_TXCOL 0x0040
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#define BIT_STAT_CLR 0xFFFF
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#define BIT_STU_SENDOVER 0x0001
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#define BIT_STU_RECVFULL 0x0020
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/*
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* All Blackfin system MMRs are padded to 32bits even if the register
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* itself is only 16bits. So use a helper macro to streamline this.
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*/
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#define __BFP(m) u16 m; u16 __pad_##m
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/*
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* bfin spi registers layout
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*/
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struct bfin_spi_regs {
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__BFP(ctl);
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__BFP(flg);
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__BFP(stat);
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__BFP(tdbr);
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__BFP(rdbr);
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__BFP(baud);
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__BFP(shadow);
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};
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#undef __BFP
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#define MAX_CTRL_CS 8 /* cs in spi controller */
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/* device.platform_data for SSP controller devices */
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struct bfin5xx_spi_master {
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u16 num_chipselect;
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u8 enable_dma;
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u16 pin_req[7];
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};
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/* spi_board_info.controller_data for SPI slave devices,
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* copied to spi_device.platform_data ... mostly for dma tuning
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*/
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struct bfin5xx_spi_chip {
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u16 ctl_reg;
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u8 enable_dma;
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u8 bits_per_word;
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u16 cs_chg_udelay; /* Some devices require 16-bit delays */
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/* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
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u16 idle_tx_val;
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u8 pio_interrupt; /* Enable spi data irq */
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};
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#endif /* _SPI_CHANNEL_H_ */
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