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715 lines
18 KiB
715 lines
18 KiB
/*
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* ata_piix.c - Intel PATA/SATA controllers
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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*
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* Copyright 2003-2005 Red Hat Inc
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* Copyright 2003-2005 Jeff Garzik
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*
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*
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* Copyright header from piix.c:
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*
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* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available at http://developer.intel.com/
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "ata_piix"
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#define DRV_VERSION "1.04"
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enum {
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PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
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ICH5_PMR = 0x90, /* port mapping register */
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ICH5_PCS = 0x92, /* port control and status */
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PIIX_SCC = 0x0A, /* sub-class code register */
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PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
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PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
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PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
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/* combined mode. if set, PATA is channel 0.
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* if clear, PATA is channel 1.
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*/
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PIIX_COMB_PATA_P0 = (1 << 1),
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PIIX_COMB = (1 << 2), /* combined mode enabled? */
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PIIX_PORT_PRESENT = (1 << 0),
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PIIX_PORT_ENABLED = (1 << 4),
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PIIX_80C_PRI = (1 << 5) | (1 << 4),
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PIIX_80C_SEC = (1 << 7) | (1 << 6),
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ich5_pata = 0,
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ich5_sata = 1,
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piix4_pata = 2,
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ich6_sata = 3,
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ich6_sata_rm = 4,
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ich7_sata = 5,
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esb2_sata = 6,
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PIIX_AHCI_DEVICE = 6,
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};
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static int piix_init_one (struct pci_dev *pdev,
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const struct pci_device_id *ent);
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static void piix_pata_phy_reset(struct ata_port *ap);
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static void piix_sata_phy_reset(struct ata_port *ap);
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static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
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static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
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static unsigned int in_module_init = 1;
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static struct pci_device_id piix_pci_tbl[] = {
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#ifdef ATA_ENABLE_PATA
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{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
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{ 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
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{ 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
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#endif
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/* NOTE: The following PCI ids must be kept in sync with the
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* list in drivers/pci/quirks.c.
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*/
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{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
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{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
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{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
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{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
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{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb2_sata },
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{ } /* terminate list */
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};
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static struct pci_driver piix_pci_driver = {
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.name = DRV_NAME,
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.id_table = piix_pci_tbl,
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.probe = piix_init_one,
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.remove = ata_pci_remove_one,
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};
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static Scsi_Host_Template piix_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.eh_strategy_handler = ata_scsi_error,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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.ordered_flush = 1,
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};
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static struct ata_port_operations piix_pata_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = piix_set_piomode,
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.set_dmamode = piix_set_dmamode,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.phy_reset = piix_pata_phy_reset,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.eng_timeout = ata_eng_timeout,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop,
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};
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static struct ata_port_operations piix_sata_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.phy_reset = piix_sata_phy_reset,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.eng_timeout = ata_eng_timeout,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop,
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};
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static struct ata_port_info piix_port_info[] = {
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/* ich5_pata */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
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PIIX_FLAG_CHECKINTR,
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.pio_mask = 0x1f, /* pio0-4 */
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#if 0
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.mwdma_mask = 0x06, /* mwdma1-2 */
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#else
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.mwdma_mask = 0x00, /* mwdma broken */
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#endif
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.udma_mask = 0x3f, /* udma0-5 */
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.port_ops = &piix_pata_ops,
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},
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/* ich5_sata */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
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PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &piix_sata_ops,
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},
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/* piix4_pata */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f, /* pio0-4 */
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#if 0
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.mwdma_mask = 0x06, /* mwdma1-2 */
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#else
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.mwdma_mask = 0x00, /* mwdma broken */
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#endif
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.udma_mask = ATA_UDMA_MASK_40C,
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.port_ops = &piix_pata_ops,
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},
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/* ich6_sata */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
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PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
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ATA_FLAG_SLAVE_POSS,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &piix_sata_ops,
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},
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/* ich6_sata_rm */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
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PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
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ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &piix_sata_ops,
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},
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/* ich7_sata */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
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PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
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ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &piix_sata_ops,
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},
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/* esb2_sata */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
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PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
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ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &piix_sata_ops,
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},
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};
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static struct pci_bits piix_enable_bits[] = {
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{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
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{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
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};
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MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
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MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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/**
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* piix_pata_cbl_detect - Probe host controller cable detect info
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* @ap: Port for which cable detect info is desired
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*
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* Read 80c cable indicator from ATA PCI device's PCI config
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* register. This register is normally set by firmware (BIOS).
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void piix_pata_cbl_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
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u8 tmp, mask;
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/* no 80c support in host controller? */
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if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
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goto cbl40;
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/* check BIOS cable detect results */
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mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
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pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
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if ((tmp & mask) == 0)
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goto cbl40;
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ap->cbl = ATA_CBL_PATA80;
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return;
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cbl40:
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ap->cbl = ATA_CBL_PATA40;
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ap->udma_mask &= ATA_UDMA_MASK_40C;
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}
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/**
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* piix_pata_phy_reset - Probe specified port on PATA host controller
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* @ap: Port to probe
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*
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* Probe PATA phy.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void piix_pata_phy_reset(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
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if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
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ata_port_disable(ap);
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printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
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return;
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}
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piix_pata_cbl_detect(ap);
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ata_port_probe(ap);
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ata_bus_reset(ap);
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}
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/**
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* piix_sata_probe - Probe PCI device for present SATA devices
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* @ap: Port associated with the PCI device we wish to probe
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*
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* Reads SATA PCI device's PCI config register Port Configuration
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* and Status (PCS) to determine port and device availability.
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*
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* LOCKING:
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* None (inherited from caller).
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*
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* RETURNS:
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* Non-zero if device detected, zero otherwise.
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*/
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static int piix_sata_probe (struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
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int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
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int orig_mask, mask, i;
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u8 pcs;
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mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
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(PIIX_PORT_ENABLED << ap->hard_port_no);
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pci_read_config_byte(pdev, ICH5_PCS, &pcs);
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orig_mask = (int) pcs & 0xff;
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/* TODO: this is vaguely wrong for ICH6 combined mode,
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* where only two of the four SATA ports are mapped
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* onto a single ATA channel. It is also vaguely inaccurate
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* for ICH5, which has only two ports. However, this is ok,
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* as further device presence detection code will handle
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* any false positives produced here.
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*/
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for (i = 0; i < 4; i++) {
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mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i);
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if ((orig_mask & mask) == mask)
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if (combined || (i == ap->hard_port_no))
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return 1;
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}
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return 0;
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}
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/**
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* piix_sata_phy_reset - Probe specified port on SATA host controller
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* @ap: Port to probe
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*
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* Probe SATA phy.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void piix_sata_phy_reset(struct ata_port *ap)
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{
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if (!piix_sata_probe(ap)) {
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ata_port_disable(ap);
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printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
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return;
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}
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ap->cbl = ATA_CBL_SATA;
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ata_port_probe(ap);
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ata_bus_reset(ap);
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}
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/**
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* piix_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: um
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* @pio: PIO mode, 0 - 4
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*
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* Set PIO mode for device, in host controller PCI config space.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio = adev->pio_mode - XFER_PIO_0;
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struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
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|
unsigned int is_slave = (adev->devno != 0);
|
|
unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
|
|
unsigned int slave_port = 0x44;
|
|
u16 master_data;
|
|
u8 slave_data;
|
|
|
|
static const /* ISP RTC */
|
|
u8 timings[][2] = { { 0, 0 },
|
|
{ 0, 0 },
|
|
{ 1, 0 },
|
|
{ 2, 1 },
|
|
{ 2, 3 }, };
|
|
|
|
pci_read_config_word(dev, master_port, &master_data);
|
|
if (is_slave) {
|
|
master_data |= 0x4000;
|
|
/* enable PPE, IE and TIME */
|
|
master_data |= 0x0070;
|
|
pci_read_config_byte(dev, slave_port, &slave_data);
|
|
slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
|
|
slave_data |=
|
|
(timings[pio][0] << 2) |
|
|
(timings[pio][1] << (ap->hard_port_no ? 4 : 0));
|
|
} else {
|
|
master_data &= 0xccf8;
|
|
/* enable PPE, IE and TIME */
|
|
master_data |= 0x0007;
|
|
master_data |=
|
|
(timings[pio][0] << 12) |
|
|
(timings[pio][1] << 8);
|
|
}
|
|
pci_write_config_word(dev, master_port, master_data);
|
|
if (is_slave)
|
|
pci_write_config_byte(dev, slave_port, slave_data);
|
|
}
|
|
|
|
/**
|
|
* piix_set_dmamode - Initialize host controller PATA PIO timings
|
|
* @ap: Port whose timings we are configuring
|
|
* @adev: um
|
|
* @udma: udma mode, 0 - 6
|
|
*
|
|
* Set UDMA mode for device, in host controller PCI config space.
|
|
*
|
|
* LOCKING:
|
|
* None (inherited from caller).
|
|
*/
|
|
|
|
static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
|
{
|
|
unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
|
|
struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
|
|
u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
|
|
u8 speed = udma;
|
|
unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
|
|
int a_speed = 3 << (drive_dn * 4);
|
|
int u_flag = 1 << drive_dn;
|
|
int v_flag = 0x01 << drive_dn;
|
|
int w_flag = 0x10 << drive_dn;
|
|
int u_speed = 0;
|
|
int sitre;
|
|
u16 reg4042, reg4a;
|
|
u8 reg48, reg54, reg55;
|
|
|
|
pci_read_config_word(dev, maslave, ®4042);
|
|
DPRINTK("reg4042 = 0x%04x\n", reg4042);
|
|
sitre = (reg4042 & 0x4000) ? 1 : 0;
|
|
pci_read_config_byte(dev, 0x48, ®48);
|
|
pci_read_config_word(dev, 0x4a, ®4a);
|
|
pci_read_config_byte(dev, 0x54, ®54);
|
|
pci_read_config_byte(dev, 0x55, ®55);
|
|
|
|
switch(speed) {
|
|
case XFER_UDMA_4:
|
|
case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
|
|
case XFER_UDMA_6:
|
|
case XFER_UDMA_5:
|
|
case XFER_UDMA_3:
|
|
case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
|
|
case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
|
|
case XFER_MW_DMA_2:
|
|
case XFER_MW_DMA_1: break;
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
|
|
if (speed >= XFER_UDMA_0) {
|
|
if (!(reg48 & u_flag))
|
|
pci_write_config_byte(dev, 0x48, reg48 | u_flag);
|
|
if (speed == XFER_UDMA_5) {
|
|
pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
|
|
} else {
|
|
pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
|
|
}
|
|
if ((reg4a & a_speed) != u_speed)
|
|
pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
|
|
if (speed > XFER_UDMA_2) {
|
|
if (!(reg54 & v_flag))
|
|
pci_write_config_byte(dev, 0x54, reg54 | v_flag);
|
|
} else
|
|
pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
|
|
} else {
|
|
if (reg48 & u_flag)
|
|
pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
|
|
if (reg4a & a_speed)
|
|
pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
|
|
if (reg54 & v_flag)
|
|
pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
|
|
if (reg55 & w_flag)
|
|
pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
|
|
}
|
|
}
|
|
|
|
/* move to PCI layer, integrate w/ MSI stuff */
|
|
static void pci_enable_intx(struct pci_dev *pdev)
|
|
{
|
|
u16 pci_command;
|
|
|
|
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
|
|
if (pci_command & PCI_COMMAND_INTX_DISABLE) {
|
|
pci_command &= ~PCI_COMMAND_INTX_DISABLE;
|
|
pci_write_config_word(pdev, PCI_COMMAND, pci_command);
|
|
}
|
|
}
|
|
|
|
#define AHCI_PCI_BAR 5
|
|
#define AHCI_GLOBAL_CTL 0x04
|
|
#define AHCI_ENABLE (1 << 31)
|
|
static int piix_disable_ahci(struct pci_dev *pdev)
|
|
{
|
|
void *mmio;
|
|
unsigned long addr;
|
|
u32 tmp;
|
|
int rc = 0;
|
|
|
|
/* BUG: pci_enable_device has not yet been called. This
|
|
* works because this device is usually set up by BIOS.
|
|
*/
|
|
|
|
addr = pci_resource_start(pdev, AHCI_PCI_BAR);
|
|
if (!addr || !pci_resource_len(pdev, AHCI_PCI_BAR))
|
|
return 0;
|
|
|
|
mmio = ioremap(addr, 64);
|
|
if (!mmio)
|
|
return -ENOMEM;
|
|
|
|
tmp = readl(mmio + AHCI_GLOBAL_CTL);
|
|
if (tmp & AHCI_ENABLE) {
|
|
tmp &= ~AHCI_ENABLE;
|
|
writel(tmp, mmio + AHCI_GLOBAL_CTL);
|
|
|
|
tmp = readl(mmio + AHCI_GLOBAL_CTL);
|
|
if (tmp & AHCI_ENABLE)
|
|
rc = -EIO;
|
|
}
|
|
|
|
iounmap(mmio);
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* piix_init_one - Register PIIX ATA PCI device with kernel services
|
|
* @pdev: PCI device to register
|
|
* @ent: Entry in piix_pci_tbl matching with @pdev
|
|
*
|
|
* Called from kernel PCI layer. We probe for combined mode (sigh),
|
|
* and then hand over control to libata, for it to do the rest.
|
|
*
|
|
* LOCKING:
|
|
* Inherited from PCI layer (may sleep).
|
|
*
|
|
* RETURNS:
|
|
* Zero on success, or -ERRNO value.
|
|
*/
|
|
|
|
static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
static int printed_version;
|
|
struct ata_port_info *port_info[2];
|
|
unsigned int combined = 0, n_ports = 1;
|
|
unsigned int pata_chan = 0, sata_chan = 0;
|
|
|
|
if (!printed_version++)
|
|
printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
|
|
|
|
/* no hotplugging support (FIXME) */
|
|
if (!in_module_init)
|
|
return -ENODEV;
|
|
|
|
port_info[0] = &piix_port_info[ent->driver_data];
|
|
port_info[1] = NULL;
|
|
|
|
if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
|
|
u8 tmp;
|
|
pci_read_config_byte(pdev, PIIX_SCC, &tmp);
|
|
if (tmp == PIIX_AHCI_DEVICE) {
|
|
int rc = piix_disable_ahci(pdev);
|
|
if (rc)
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
|
|
u8 tmp;
|
|
pci_read_config_byte(pdev, ICH5_PMR, &tmp);
|
|
|
|
if (tmp & PIIX_COMB) {
|
|
combined = 1;
|
|
if (tmp & PIIX_COMB_PATA_P0)
|
|
sata_chan = 1;
|
|
else
|
|
pata_chan = 1;
|
|
}
|
|
}
|
|
|
|
/* On ICH5, some BIOSen disable the interrupt using the
|
|
* PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
|
|
* On ICH6, this bit has the same effect, but only when
|
|
* MSI is disabled (and it is disabled, as we don't use
|
|
* message-signalled interrupts currently).
|
|
*/
|
|
if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
|
|
pci_enable_intx(pdev);
|
|
|
|
if (combined) {
|
|
port_info[sata_chan] = &piix_port_info[ent->driver_data];
|
|
port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
|
|
port_info[pata_chan] = &piix_port_info[ich5_pata];
|
|
n_ports++;
|
|
|
|
printk(KERN_WARNING DRV_NAME ": combined mode detected\n");
|
|
}
|
|
|
|
return ata_pci_init_one(pdev, port_info, n_ports);
|
|
}
|
|
|
|
static int __init piix_init(void)
|
|
{
|
|
int rc;
|
|
|
|
DPRINTK("pci_module_init\n");
|
|
rc = pci_module_init(&piix_pci_driver);
|
|
if (rc)
|
|
return rc;
|
|
|
|
in_module_init = 0;
|
|
|
|
DPRINTK("done\n");
|
|
return 0;
|
|
}
|
|
|
|
static void __exit piix_exit(void)
|
|
{
|
|
pci_unregister_driver(&piix_pci_driver);
|
|
}
|
|
|
|
module_init(piix_init);
|
|
module_exit(piix_exit);
|
|
|
|
|