You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
704 lines
15 KiB
704 lines
15 KiB
/*
|
|
* P2020 DS Device Tree Source
|
|
*
|
|
* Copyright 2009 Freescale Semiconductor Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
/ {
|
|
model = "fsl,P2020";
|
|
compatible = "fsl,P2020DS";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
aliases {
|
|
ethernet0 = &enet0;
|
|
ethernet1 = &enet1;
|
|
ethernet2 = &enet2;
|
|
serial0 = &serial0;
|
|
serial1 = &serial1;
|
|
pci0 = &pci0;
|
|
pci1 = &pci1;
|
|
pci2 = &pci2;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
PowerPC,P2020@0 {
|
|
device_type = "cpu";
|
|
reg = <0x0>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
|
|
PowerPC,P2020@1 {
|
|
device_type = "cpu";
|
|
reg = <0x1>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
};
|
|
|
|
localbus@ffe05000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,elbc", "simple-bus";
|
|
reg = <0 0xffe05000 0 0x1000>;
|
|
interrupts = <19 2>;
|
|
interrupt-parent = <&mpic>;
|
|
|
|
ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
|
|
0x1 0x0 0x0 0xe0000000 0x08000000
|
|
0x2 0x0 0x0 0xffa00000 0x00040000
|
|
0x3 0x0 0x0 0xffdf0000 0x00008000
|
|
0x4 0x0 0x0 0xffa40000 0x00040000
|
|
0x5 0x0 0x0 0xffa80000 0x00040000
|
|
0x6 0x0 0x0 0xffac0000 0x00040000>;
|
|
|
|
nor@0,0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "cfi-flash";
|
|
reg = <0x0 0x0 0x8000000>;
|
|
bank-width = <2>;
|
|
device-width = <1>;
|
|
|
|
ramdisk@0 {
|
|
reg = <0x0 0x03000000>;
|
|
read-only;
|
|
};
|
|
|
|
diagnostic@3000000 {
|
|
reg = <0x03000000 0x00e00000>;
|
|
read-only;
|
|
};
|
|
|
|
dink@3e00000 {
|
|
reg = <0x03e00000 0x00200000>;
|
|
read-only;
|
|
};
|
|
|
|
kernel@4000000 {
|
|
reg = <0x04000000 0x00400000>;
|
|
read-only;
|
|
};
|
|
|
|
jffs2@4400000 {
|
|
reg = <0x04400000 0x03b00000>;
|
|
};
|
|
|
|
dtb@7f00000 {
|
|
reg = <0x07f00000 0x00080000>;
|
|
read-only;
|
|
};
|
|
|
|
u-boot@7f80000 {
|
|
reg = <0x07f80000 0x00080000>;
|
|
read-only;
|
|
};
|
|
};
|
|
|
|
nand@2,0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,elbc-fcm-nand";
|
|
reg = <0x2 0x0 0x40000>;
|
|
|
|
u-boot@0 {
|
|
reg = <0x0 0x02000000>;
|
|
read-only;
|
|
};
|
|
|
|
jffs2@2000000 {
|
|
reg = <0x02000000 0x10000000>;
|
|
};
|
|
|
|
ramdisk@12000000 {
|
|
reg = <0x12000000 0x08000000>;
|
|
read-only;
|
|
};
|
|
|
|
kernel@1a000000 {
|
|
reg = <0x1a000000 0x04000000>;
|
|
};
|
|
|
|
dtb@1e000000 {
|
|
reg = <0x1e000000 0x01000000>;
|
|
read-only;
|
|
};
|
|
|
|
empty@1f000000 {
|
|
reg = <0x1f000000 0x21000000>;
|
|
};
|
|
};
|
|
|
|
nand@4,0 {
|
|
compatible = "fsl,elbc-fcm-nand";
|
|
reg = <0x4 0x0 0x40000>;
|
|
};
|
|
|
|
nand@5,0 {
|
|
compatible = "fsl,elbc-fcm-nand";
|
|
reg = <0x5 0x0 0x40000>;
|
|
};
|
|
|
|
nand@6,0 {
|
|
compatible = "fsl,elbc-fcm-nand";
|
|
reg = <0x6 0x0 0x40000>;
|
|
};
|
|
};
|
|
|
|
soc@ffe00000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
compatible = "fsl,p2020-immr", "simple-bus";
|
|
ranges = <0x0 0 0xffe00000 0x100000>;
|
|
bus-frequency = <0>; // Filled out by uboot.
|
|
|
|
ecm-law@0 {
|
|
compatible = "fsl,ecm-law";
|
|
reg = <0x0 0x1000>;
|
|
fsl,num-laws = <12>;
|
|
};
|
|
|
|
ecm@1000 {
|
|
compatible = "fsl,p2020-ecm", "fsl,ecm";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <17 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
memory-controller@2000 {
|
|
compatible = "fsl,p2020-memory-controller";
|
|
reg = <0x2000 0x1000>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <18 2>;
|
|
};
|
|
|
|
i2c@3000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
compatible = "fsl-i2c";
|
|
reg = <0x3000 0x100>;
|
|
interrupts = <43 2>;
|
|
interrupt-parent = <&mpic>;
|
|
dfsrr;
|
|
};
|
|
|
|
i2c@3100 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <1>;
|
|
compatible = "fsl-i2c";
|
|
reg = <0x3100 0x100>;
|
|
interrupts = <43 2>;
|
|
interrupt-parent = <&mpic>;
|
|
dfsrr;
|
|
};
|
|
|
|
serial0: serial@4500 {
|
|
cell-index = <0>;
|
|
device_type = "serial";
|
|
compatible = "ns16550";
|
|
reg = <0x4500 0x100>;
|
|
clock-frequency = <0>;
|
|
interrupts = <42 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
serial1: serial@4600 {
|
|
cell-index = <1>;
|
|
device_type = "serial";
|
|
compatible = "ns16550";
|
|
reg = <0x4600 0x100>;
|
|
clock-frequency = <0>;
|
|
interrupts = <42 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
spi@7000 {
|
|
compatible = "fsl,espi";
|
|
reg = <0x7000 0x1000>;
|
|
interrupts = <59 0x2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
dma@c300 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,eloplus-dma";
|
|
reg = <0xc300 0x4>;
|
|
ranges = <0x0 0xc100 0x200>;
|
|
cell-index = <1>;
|
|
dma-channel@0 {
|
|
compatible = "fsl,eloplus-dma-channel";
|
|
reg = <0x0 0x80>;
|
|
cell-index = <0>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <76 2>;
|
|
};
|
|
dma-channel@80 {
|
|
compatible = "fsl,eloplus-dma-channel";
|
|
reg = <0x80 0x80>;
|
|
cell-index = <1>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <77 2>;
|
|
};
|
|
dma-channel@100 {
|
|
compatible = "fsl,eloplus-dma-channel";
|
|
reg = <0x100 0x80>;
|
|
cell-index = <2>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <78 2>;
|
|
};
|
|
dma-channel@180 {
|
|
compatible = "fsl,eloplus-dma-channel";
|
|
reg = <0x180 0x80>;
|
|
cell-index = <3>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <79 2>;
|
|
};
|
|
};
|
|
|
|
gpio: gpio-controller@f000 {
|
|
#gpio-cells = <2>;
|
|
compatible = "fsl,mpc8572-gpio";
|
|
reg = <0xf000 0x100>;
|
|
interrupts = <47 0x2>;
|
|
interrupt-parent = <&mpic>;
|
|
gpio-controller;
|
|
};
|
|
|
|
L2: l2-cache-controller@20000 {
|
|
compatible = "fsl,p2020-l2-cache-controller";
|
|
reg = <0x20000 0x1000>;
|
|
cache-line-size = <32>; // 32 bytes
|
|
cache-size = <0x80000>; // L2, 512k
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <16 2>;
|
|
};
|
|
|
|
dma@21300 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,eloplus-dma";
|
|
reg = <0x21300 0x4>;
|
|
ranges = <0x0 0x21100 0x200>;
|
|
cell-index = <0>;
|
|
dma-channel@0 {
|
|
compatible = "fsl,eloplus-dma-channel";
|
|
reg = <0x0 0x80>;
|
|
cell-index = <0>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <20 2>;
|
|
};
|
|
dma-channel@80 {
|
|
compatible = "fsl,eloplus-dma-channel";
|
|
reg = <0x80 0x80>;
|
|
cell-index = <1>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <21 2>;
|
|
};
|
|
dma-channel@100 {
|
|
compatible = "fsl,eloplus-dma-channel";
|
|
reg = <0x100 0x80>;
|
|
cell-index = <2>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <22 2>;
|
|
};
|
|
dma-channel@180 {
|
|
compatible = "fsl,eloplus-dma-channel";
|
|
reg = <0x180 0x80>;
|
|
cell-index = <3>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <23 2>;
|
|
};
|
|
};
|
|
|
|
usb@22000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl-usb2-dr";
|
|
reg = <0x22000 0x1000>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <28 0x2>;
|
|
phy_type = "ulpi";
|
|
};
|
|
|
|
enet0: ethernet@24000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
cell-index = <0>;
|
|
device_type = "network";
|
|
model = "eTSEC";
|
|
compatible = "gianfar";
|
|
reg = <0x24000 0x1000>;
|
|
ranges = <0x0 0x24000 0x1000>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <29 2 30 2 34 2>;
|
|
interrupt-parent = <&mpic>;
|
|
tbi-handle = <&tbi0>;
|
|
phy-handle = <&phy0>;
|
|
phy-connection-type = "rgmii-id";
|
|
|
|
mdio@520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,gianfar-mdio";
|
|
reg = <0x520 0x20>;
|
|
|
|
phy0: ethernet-phy@0 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <3 1>;
|
|
reg = <0x0>;
|
|
};
|
|
phy1: ethernet-phy@1 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <3 1>;
|
|
reg = <0x1>;
|
|
};
|
|
phy2: ethernet-phy@2 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <3 1>;
|
|
reg = <0x2>;
|
|
};
|
|
tbi0: tbi-phy@11 {
|
|
reg = <0x11>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
};
|
|
|
|
enet1: ethernet@25000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
cell-index = <1>;
|
|
device_type = "network";
|
|
model = "eTSEC";
|
|
compatible = "gianfar";
|
|
reg = <0x25000 0x1000>;
|
|
ranges = <0x0 0x25000 0x1000>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <35 2 36 2 40 2>;
|
|
interrupt-parent = <&mpic>;
|
|
tbi-handle = <&tbi1>;
|
|
phy-handle = <&phy1>;
|
|
phy-connection-type = "rgmii-id";
|
|
|
|
mdio@520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,gianfar-tbi";
|
|
reg = <0x520 0x20>;
|
|
|
|
tbi1: tbi-phy@11 {
|
|
reg = <0x11>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
};
|
|
|
|
enet2: ethernet@26000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
cell-index = <2>;
|
|
device_type = "network";
|
|
model = "eTSEC";
|
|
compatible = "gianfar";
|
|
reg = <0x26000 0x1000>;
|
|
ranges = <0x0 0x26000 0x1000>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <31 2 32 2 33 2>;
|
|
interrupt-parent = <&mpic>;
|
|
tbi-handle = <&tbi2>;
|
|
phy-handle = <&phy2>;
|
|
phy-connection-type = "rgmii-id";
|
|
|
|
mdio@520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,gianfar-tbi";
|
|
reg = <0x520 0x20>;
|
|
|
|
tbi2: tbi-phy@11 {
|
|
reg = <0x11>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
};
|
|
|
|
sdhci@2e000 {
|
|
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
|
|
reg = <0x2e000 0x1000>;
|
|
interrupts = <72 0x2>;
|
|
interrupt-parent = <&mpic>;
|
|
/* Filled in by U-Boot */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
crypto@30000 {
|
|
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
|
|
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
|
reg = <0x30000 0x10000>;
|
|
interrupts = <45 2 58 2>;
|
|
interrupt-parent = <&mpic>;
|
|
fsl,num-channels = <4>;
|
|
fsl,channel-fifo-len = <24>;
|
|
fsl,exec-units-mask = <0xbfe>;
|
|
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
|
};
|
|
|
|
mpic: pic@40000 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x40000 0x40000>;
|
|
compatible = "chrp,open-pic";
|
|
device_type = "open-pic";
|
|
};
|
|
|
|
msi@41600 {
|
|
compatible = "fsl,mpic-msi";
|
|
reg = <0x41600 0x80>;
|
|
msi-available-ranges = <0 0x100>;
|
|
interrupts = <
|
|
0xe0 0
|
|
0xe1 0
|
|
0xe2 0
|
|
0xe3 0
|
|
0xe4 0
|
|
0xe5 0
|
|
0xe6 0
|
|
0xe7 0>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
global-utilities@e0000 { //global utilities block
|
|
compatible = "fsl,p2020-guts";
|
|
reg = <0xe0000 0x1000>;
|
|
fsl,has-rstcr;
|
|
};
|
|
};
|
|
|
|
pci0: pcie@ffe08000 {
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0 0xffe08000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <24 2>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0x0 0x0 0x1 &mpic 0x8 0x1
|
|
0000 0x0 0x0 0x2 &mpic 0x9 0x1
|
|
0000 0x0 0x0 0x3 &mpic 0xa 0x1
|
|
0000 0x0 0x0 0x4 &mpic 0xb 0x1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0x80000000
|
|
0x2000000 0x0 0x80000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x10000>;
|
|
};
|
|
};
|
|
|
|
pci1: pcie@ffe09000 {
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0 0xffe09000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <25 2>;
|
|
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
|
|
// IDSEL 0x11 func 0 - PCI slot 1
|
|
0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
|
|
0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
|
|
|
|
// IDSEL 0x11 func 1 - PCI slot 1
|
|
0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
|
|
0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
|
|
|
|
// IDSEL 0x11 func 2 - PCI slot 1
|
|
0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
|
|
0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
|
|
|
|
// IDSEL 0x11 func 3 - PCI slot 1
|
|
0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
|
|
0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
|
|
|
|
// IDSEL 0x11 func 4 - PCI slot 1
|
|
0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
|
|
0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
|
|
|
|
// IDSEL 0x11 func 5 - PCI slot 1
|
|
0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
|
|
0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
|
|
|
|
// IDSEL 0x11 func 6 - PCI slot 1
|
|
0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
|
|
0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
|
|
|
|
// IDSEL 0x11 func 7 - PCI slot 1
|
|
0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
|
|
0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
|
|
|
|
// IDSEL 0x1d Audio
|
|
0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
|
|
|
|
// IDSEL 0x1e Legacy
|
|
0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
|
|
0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
|
|
|
|
// IDSEL 0x1f IDE/SATA
|
|
0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
|
|
0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
|
|
>;
|
|
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xa0000000
|
|
0x2000000 0x0 0xa0000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x10000>;
|
|
uli1575@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
ranges = <0x2000000 0x0 0xa0000000
|
|
0x2000000 0x0 0xa0000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x10000>;
|
|
isa@1e {
|
|
device_type = "isa";
|
|
#interrupt-cells = <2>;
|
|
#size-cells = <1>;
|
|
#address-cells = <2>;
|
|
reg = <0xf000 0x0 0x0 0x0 0x0>;
|
|
ranges = <0x1 0x0 0x1000000 0x0 0x0
|
|
0x1000>;
|
|
interrupt-parent = <&i8259>;
|
|
|
|
i8259: interrupt-controller@20 {
|
|
reg = <0x1 0x20 0x2
|
|
0x1 0xa0 0x2
|
|
0x1 0x4d0 0x2>;
|
|
interrupt-controller;
|
|
device_type = "interrupt-controller";
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
compatible = "chrp,iic";
|
|
interrupts = <4 1>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
i8042@60 {
|
|
#size-cells = <0>;
|
|
#address-cells = <1>;
|
|
reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
|
|
interrupts = <1 3 12 3>;
|
|
interrupt-parent =
|
|
<&i8259>;
|
|
|
|
keyboard@0 {
|
|
reg = <0x0>;
|
|
compatible = "pnpPNP,303";
|
|
};
|
|
|
|
mouse@1 {
|
|
reg = <0x1>;
|
|
compatible = "pnpPNP,f03";
|
|
};
|
|
};
|
|
|
|
rtc@70 {
|
|
compatible = "pnpPNP,b00";
|
|
reg = <0x1 0x70 0x2>;
|
|
};
|
|
|
|
gpio@400 {
|
|
reg = <0x1 0x400 0x80>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
pci2: pcie@ffe0a000 {
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0 0xffe0a000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <26 2>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
|
0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
|
0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
|
0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xc0000000
|
|
0x2000000 0x0 0xc0000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x10000>;
|
|
};
|
|
};
|
|
};
|
|
|