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76 lines
2.0 KiB
76 lines
2.0 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __DTS_MARVELL_MMP2_CLOCK_H
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#define __DTS_MARVELL_MMP2_CLOCK_H
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/* fixed clocks and plls */
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#define MMP2_CLK_CLK32 1
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#define MMP2_CLK_VCTCXO 2
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#define MMP2_CLK_PLL1 3
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#define MMP2_CLK_PLL1_2 8
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#define MMP2_CLK_PLL1_4 9
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#define MMP2_CLK_PLL1_8 10
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#define MMP2_CLK_PLL1_16 11
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#define MMP2_CLK_PLL1_3 12
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#define MMP2_CLK_PLL1_6 13
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#define MMP2_CLK_PLL1_12 14
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#define MMP2_CLK_PLL1_20 15
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#define MMP2_CLK_PLL2 16
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#define MMP2_CLK_PLL2_2 17
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#define MMP2_CLK_PLL2_4 18
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#define MMP2_CLK_PLL2_8 19
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#define MMP2_CLK_PLL2_16 20
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#define MMP2_CLK_PLL2_3 21
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#define MMP2_CLK_PLL2_6 22
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#define MMP2_CLK_PLL2_12 23
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#define MMP2_CLK_VCTCXO_2 24
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#define MMP2_CLK_VCTCXO_4 25
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#define MMP2_CLK_UART_PLL 26
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#define MMP2_CLK_USB_PLL 27
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/* apb periphrals */
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#define MMP2_CLK_TWSI0 60
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#define MMP2_CLK_TWSI1 61
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#define MMP2_CLK_TWSI2 62
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#define MMP2_CLK_TWSI3 63
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#define MMP2_CLK_TWSI4 64
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#define MMP2_CLK_TWSI5 65
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#define MMP2_CLK_GPIO 66
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#define MMP2_CLK_KPC 67
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#define MMP2_CLK_RTC 68
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#define MMP2_CLK_PWM0 69
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#define MMP2_CLK_PWM1 70
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#define MMP2_CLK_PWM2 71
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#define MMP2_CLK_PWM3 72
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#define MMP2_CLK_UART0 73
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#define MMP2_CLK_UART1 74
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#define MMP2_CLK_UART2 75
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#define MMP2_CLK_UART3 76
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#define MMP2_CLK_SSP0 77
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#define MMP2_CLK_SSP1 78
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#define MMP2_CLK_SSP2 79
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#define MMP2_CLK_SSP3 80
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#define MMP2_CLK_TIMER 81
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/* axi periphrals */
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#define MMP2_CLK_SDH0 101
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#define MMP2_CLK_SDH1 102
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#define MMP2_CLK_SDH2 103
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#define MMP2_CLK_SDH3 104
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#define MMP2_CLK_USB 105
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#define MMP2_CLK_DISP0 106
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#define MMP2_CLK_DISP0_MUX 107
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#define MMP2_CLK_DISP0_SPHY 108
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#define MMP2_CLK_DISP1 109
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#define MMP2_CLK_DISP1_MUX 110
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#define MMP2_CLK_CCIC_ARBITER 111
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#define MMP2_CLK_CCIC0 112
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#define MMP2_CLK_CCIC0_MIX 113
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#define MMP2_CLK_CCIC0_PHY 114
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#define MMP2_CLK_CCIC0_SPHY 115
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#define MMP2_CLK_CCIC1 116
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#define MMP2_CLK_CCIC1_MIX 117
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#define MMP2_CLK_CCIC1_PHY 118
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#define MMP2_CLK_CCIC1_SPHY 119
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#define MMP2_NR_CLKS 200
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#endif
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