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98 lines
3.5 KiB
98 lines
3.5 KiB
/*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _I915_DRM_H_
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#define _I915_DRM_H_
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#include <drm/i915_pciids.h>
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#include <uapi/drm/i915_drm.h>
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/* For use by IPS driver */
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extern unsigned long i915_read_mch_val(void);
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extern bool i915_gpu_raise(void);
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extern bool i915_gpu_lower(void);
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extern bool i915_gpu_busy(void);
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extern bool i915_gpu_turbo_disable(void);
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/*
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* The Bridge device's PCI config space has information about the
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* fb aperture size and the amount of pre-reserved memory.
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* This is all handled in the intel-gtt.ko module. i915.ko only
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* cares about the vga bit for the vga rbiter.
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*/
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#define INTEL_GMCH_CTRL 0x52
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#define INTEL_GMCH_VGA_DISABLE (1 << 1)
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#define SNB_GMCH_CTRL 0x50
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#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
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#define SNB_GMCH_GGMS_MASK 0x3
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#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
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#define SNB_GMCH_GMS_MASK 0x1f
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#define BDW_GMCH_GGMS_SHIFT 6
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#define BDW_GMCH_GGMS_MASK 0x3
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#define BDW_GMCH_GMS_SHIFT 8
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#define BDW_GMCH_GMS_MASK 0xff
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#define I830_GMCH_CTRL 0x52
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#define I830_GMCH_GMS_MASK 0x70
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#define I830_GMCH_GMS_LOCAL 0x10
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#define I830_GMCH_GMS_STOLEN_512 0x20
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#define I830_GMCH_GMS_STOLEN_1024 0x30
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#define I830_GMCH_GMS_STOLEN_8192 0x40
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#define I855_GMCH_GMS_MASK 0xF0
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#define I855_GMCH_GMS_STOLEN_0M 0x0
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#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
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#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
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#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
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#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
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#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
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#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
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#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
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#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
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#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
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#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
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#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
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#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
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#define I830_DRB3 0x63
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#define I85X_DRB3 0x43
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#define I865_TOUD 0xc4
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#define I830_ESMRAMC 0x91
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#define I845_ESMRAMC 0x9e
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#define I85X_ESMRAMC 0x61
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#define TSEG_ENABLE (1 << 0)
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#define I830_TSEG_SIZE_512K (0 << 1)
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#define I830_TSEG_SIZE_1M (1 << 1)
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#define I845_TSEG_SIZE_MASK (3 << 1)
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#define I845_TSEG_SIZE_512K (2 << 1)
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#define I845_TSEG_SIZE_1M (3 << 1)
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#define INTEL_BSM 0x5c
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#define INTEL_BSM_MASK (-(1u << 20))
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#endif /* _I915_DRM_H_ */
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