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731 lines
18 KiB
731 lines
18 KiB
/* Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* MSM PCIe MSI controller
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*/
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#include <linux/interrupt.h>
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#include <linux/iommu.h>
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#include <linux/ipc_logging.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/msi.h>
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#include <linux/msm_pcie.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#define PCIE_MSI_CTRL_BASE (0x820)
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#define PCIE_MSI_CTRL_ADDR_OFFS (PCIE_MSI_CTRL_BASE)
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#define PCIE_MSI_CTRL_UPPER_ADDR_OFFS (PCIE_MSI_CTRL_BASE + 0x4)
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#define PCIE_MSI_CTRL_INT_N_EN_OFFS(n) (PCIE_MSI_CTRL_BASE + 0x8 + 0xc * n)
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#define PCIE_MSI_CTRL_INT_N_MASK_OFFS(n) (PCIE_MSI_CTRL_BASE + 0xc + 0xc * n)
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#define PCIE_MSI_CTRL_INT_N_STATUS_OFFS(n) (PCIE_MSI_CTRL_BASE + 0x10 + 0xc * n)
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#define MSI_IRQ_PER_GRP (32)
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enum msi_type {
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MSM_MSI_TYPE_QCOM,
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MSM_MSI_TYPE_SNPS,
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};
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struct msm_msi_irq {
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struct msm_msi_client *client;
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struct msm_msi_grp *grp; /* group the irq belongs to */
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u32 grp_index; /* index in the group */
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unsigned int hwirq; /* MSI controller hwirq */
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unsigned int virq; /* MSI controller virq */
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u32 pos; /* position in MSI bitmap */
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};
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struct msm_msi_grp {
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/* registers for SNPS only */
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void __iomem *int_en_reg;
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void __iomem *int_mask_reg;
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void __iomem *int_status_reg;
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u32 mask; /* tracks masked/unmasked MSI */
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struct msm_msi_irq irqs[MSI_IRQ_PER_GRP];
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};
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struct msm_msi {
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struct list_head clients;
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struct device *dev;
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struct device_node *of_node;
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int nr_hwirqs;
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int nr_virqs;
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int nr_grps;
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struct msm_msi_grp *grps;
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unsigned long *bitmap; /* tracks used/unused MSI */
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struct mutex mutex; /* mutex for modifying MSI client list and bitmap */
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struct irq_domain *inner_domain; /* parent domain; gen irq related */
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struct irq_domain *msi_domain; /* child domain; pci related */
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phys_addr_t msi_addr;
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enum msi_type type;
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spinlock_t cfg_lock; /* lock for configuring Synopsys MSI registers */
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bool cfg_access; /* control access to MSI registers */
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void __iomem *pcie_cfg;
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void (*mask_irq)(struct irq_data *data);
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void (*unmask_irq)(struct irq_data *data);
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};
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/* structure for each client of MSI controller */
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struct msm_msi_client {
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struct list_head node;
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struct msm_msi *msi;
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struct device *dev; /* client's dev of pci_dev */
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u32 nr_irqs; /* nr_irqs allocated for client */
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dma_addr_t msi_addr;
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};
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static void msm_msi_snps_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct msm_msi_grp *msi_grp;
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int i;
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u32 status, mask;
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chained_irq_enter(chip, desc);
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msi_grp = irq_desc_get_handler_data(desc);
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status = readl_relaxed(msi_grp->int_status_reg);
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/* always update the mask set in msm_msi_snps_mask_irq */
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mask = msi_grp->mask;
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writel_relaxed(mask, msi_grp->int_mask_reg);
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/* process only interrupts which are not masked */
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status ^= (status & mask);
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writel_relaxed(status, msi_grp->int_status_reg);
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for (i = 0; status; i++, status >>= 1)
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if (status & 0x1)
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generic_handle_irq(msi_grp->irqs[i].virq);
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chained_irq_exit(chip, desc);
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}
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static void msm_msi_qgic_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct msm_msi *msi;
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unsigned int virq;
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chained_irq_enter(chip, desc);
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msi = irq_desc_get_handler_data(desc);
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virq = irq_find_mapping(msi->inner_domain, irq_desc_get_irq(desc));
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generic_handle_irq(virq);
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chained_irq_exit(chip, desc);
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}
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static void msm_msi_snps_mask_irq(struct irq_data *data)
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{
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struct msm_msi_irq *msi_irq = irq_data_get_irq_chip_data(data);
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struct msm_msi_grp *msi_grp = msi_irq->grp;
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struct msm_msi *msi = msi_irq->client->msi;
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unsigned long flags;
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spin_lock_irqsave(&msi->cfg_lock, flags);
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msi_grp->mask |= BIT(msi_irq->grp_index);
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spin_unlock_irqrestore(&msi->cfg_lock, flags);
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}
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static void msm_msi_qgic_mask_irq(struct irq_data *data)
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{
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struct irq_data *parent_data;
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parent_data = irq_get_irq_data(irqd_to_hwirq(data));
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if (!parent_data || !parent_data->chip)
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return;
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parent_data->chip->irq_mask(parent_data);
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}
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static void msm_msi_mask_irq(struct irq_data *data)
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{
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struct irq_data *parent_data;
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struct msm_msi_irq *msi_irq;
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struct msm_msi *msi;
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unsigned long flags;
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parent_data = data->parent_data;
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if (!parent_data)
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return;
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msi_irq = irq_data_get_irq_chip_data(parent_data);
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msi = msi_irq->client->msi;
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spin_lock_irqsave(&msi->cfg_lock, flags);
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if (msi->cfg_access)
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pci_msi_mask_irq(data);
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spin_unlock_irqrestore(&msi->cfg_lock, flags);
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msi->mask_irq(parent_data);
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}
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static void msm_msi_snps_unmask_irq(struct irq_data *data)
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{
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struct msm_msi_irq *msi_irq = irq_data_get_irq_chip_data(data);
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struct msm_msi_grp *msi_grp = msi_irq->grp;
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struct msm_msi *msi = msi_irq->client->msi;
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unsigned long flags;
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spin_lock_irqsave(&msi->cfg_lock, flags);
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msi_grp->mask &= ~BIT(msi_irq->grp_index);
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if (msi->cfg_access)
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writel_relaxed(msi_grp->mask, msi_grp->int_mask_reg);
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spin_unlock_irqrestore(&msi->cfg_lock, flags);
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}
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static void msm_msi_qgic_unmask_irq(struct irq_data *data)
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{
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struct irq_data *parent_data;
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parent_data = irq_get_irq_data(irqd_to_hwirq(data));
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if (!parent_data || !parent_data->chip)
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return;
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parent_data->chip->irq_unmask(parent_data);
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}
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static void msm_msi_unmask_irq(struct irq_data *data)
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{
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struct irq_data *parent_data;
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struct msm_msi_irq *msi_irq;
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struct msm_msi *msi;
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unsigned long flags;
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parent_data = data->parent_data;
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if (!parent_data)
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return;
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msi_irq = irq_data_get_irq_chip_data(parent_data);
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msi = msi_irq->client->msi;
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msi->unmask_irq(parent_data);
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spin_lock_irqsave(&msi->cfg_lock, flags);
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if (msi->cfg_access)
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pci_msi_unmask_irq(data);
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spin_unlock_irqrestore(&msi->cfg_lock, flags);
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}
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static struct irq_chip msm_msi_irq_chip = {
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.name = "msm_pci_msi",
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.irq_enable = msm_msi_unmask_irq,
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.irq_disable = msm_msi_mask_irq,
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.irq_mask = msm_msi_mask_irq,
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.irq_unmask = msm_msi_unmask_irq,
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};
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static int msm_msi_domain_prepare(struct irq_domain *domain, struct device *dev,
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int nvec, msi_alloc_info_t *arg)
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{
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struct msm_msi *msi = domain->parent->host_data;
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struct msm_msi_client *client;
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client = devm_kzalloc(msi->dev, sizeof(*client), GFP_KERNEL);
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if (!client)
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return -ENOMEM;
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client->msi = msi;
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client->dev = dev;
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client->msi_addr = msi->msi_addr;
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/*
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* Accesses to QGIC MSI doorbell register goes through PCIe SMMU and
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* needs to be mapped. Synopsys MSI doorbell is within the PCIe core
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* and does not need to be mapped.
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*/
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if (msi->type == MSM_MSI_TYPE_QCOM) {
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client->msi_addr = dma_map_resource(client->dev, msi->msi_addr,
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PAGE_SIZE, DMA_FROM_DEVICE, 0);
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if (dma_mapping_error(client->dev, client->msi_addr)) {
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dev_err(msi->dev, "MSI: failed to map msi address\n");
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client->msi_addr = 0;
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return -ENOMEM;
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}
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}
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mutex_lock(&msi->mutex);
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list_add_tail(&client->node, &msi->clients);
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mutex_unlock(&msi->mutex);
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/* zero out struct for framework */
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memset(arg, 0, sizeof(*arg));
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return 0;
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}
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void msm_msi_domain_finish(msi_alloc_info_t *arg, int retval)
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{
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struct device *dev = arg->desc->dev;
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struct irq_domain *domain = dev_get_msi_domain(dev);
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struct msm_msi *msi = domain->parent->host_data;
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/* if prepare or alloc fails, then clean up */
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if (retval) {
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struct msm_msi_client *tmp, *client = NULL;
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mutex_lock(&msi->mutex);
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list_for_each_entry(tmp, &msi->clients, node) {
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if (tmp->dev == dev) {
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client = tmp;
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list_del(&client->node);
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break;
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}
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}
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mutex_unlock(&msi->mutex);
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if (!client)
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return;
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if ((msi->type == MSM_MSI_TYPE_QCOM) && client->msi_addr)
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dma_unmap_resource(client->dev, client->msi_addr,
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PAGE_SIZE, DMA_FROM_DEVICE, 0);
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devm_kfree(msi->dev, client);
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return;
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}
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}
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static struct msi_domain_ops msm_msi_domain_ops = {
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.msi_prepare = msm_msi_domain_prepare,
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.msi_finish = msm_msi_domain_finish,
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};
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static struct msi_domain_info msm_msi_domain_info = {
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.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
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.ops = &msm_msi_domain_ops,
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.chip = &msm_msi_irq_chip,
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};
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static int msm_msi_irq_set_affinity(struct irq_data *data,
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const struct cpumask *mask, bool force)
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{
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struct irq_data *parent_data = irq_get_irq_data(irqd_to_hwirq(data));
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if (!parent_data)
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return -ENODEV;
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/* set affinity for MSM MSI HW IRQ */
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if (parent_data->chip->irq_set_affinity)
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return parent_data->chip->irq_set_affinity(parent_data,
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mask, force);
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return -EINVAL;
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}
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static void msm_msi_irq_compose_msi_msg(struct irq_data *data,
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struct msi_msg *msg)
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{
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struct msm_msi_irq *msi_irq = irq_data_get_irq_chip_data(data);
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struct irq_data *parent_data = irq_get_irq_data(irqd_to_hwirq(data));
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struct msm_msi_client *client = msi_irq->client;
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struct msm_msi *msi = client->msi;
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if (!parent_data)
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return;
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msg->address_lo = lower_32_bits(client->msi_addr);
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msg->address_hi = upper_32_bits(client->msi_addr);
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msg->data = (msi->type == MSM_MSI_TYPE_QCOM) ?
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irqd_to_hwirq(parent_data) : msi_irq->pos;
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}
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static struct irq_chip msm_msi_bottom_irq_chip = {
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.name = "msm_msi",
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.irq_set_affinity = msm_msi_irq_set_affinity,
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.irq_compose_msi_msg = msm_msi_irq_compose_msi_msg,
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};
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static int msm_msi_irq_domain_alloc(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs,
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void *args)
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{
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struct msm_msi *msi = domain->host_data;
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struct msm_msi_client *tmp, *client = NULL;
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struct device *dev = ((msi_alloc_info_t *)args)->desc->dev;
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int i, ret = 0;
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int pos;
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mutex_lock(&msi->mutex);
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list_for_each_entry(tmp, &msi->clients, node) {
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if (tmp->dev == dev) {
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client = tmp;
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break;
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}
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}
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if (!client) {
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dev_err(msi->dev, "MSI: failed to find client dev\n");
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ret = -ENODEV;
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goto out;
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}
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pos = bitmap_find_next_zero_area(msi->bitmap, msi->nr_virqs, 0,
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nr_irqs, nr_irqs - 1);
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if (pos < msi->nr_virqs) {
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bitmap_set(msi->bitmap, pos, nr_irqs);
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} else {
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ret = -ENOSPC;
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goto out;
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}
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for (i = 0; i < nr_irqs; i++) {
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u32 grp = pos / MSI_IRQ_PER_GRP;
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u32 index = pos % MSI_IRQ_PER_GRP;
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struct msm_msi_irq *msi_irq = &msi->grps[grp].irqs[index];
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msi_irq->virq = virq + i;
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msi_irq->client = client;
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irq_domain_set_info(domain, msi_irq->virq,
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msi_irq->hwirq,
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&msm_msi_bottom_irq_chip, msi_irq,
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handle_simple_irq, NULL, NULL);
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client->nr_irqs++;
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pos++;
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}
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out:
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mutex_unlock(&msi->mutex);
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return ret;
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}
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static void msm_msi_irq_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *data = irq_domain_get_irq_data(domain, virq);
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struct msm_msi_irq *msi_irq;
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struct msm_msi_client *client;
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struct msm_msi *msi;
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if (!data)
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return;
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msi_irq = irq_data_get_irq_chip_data(data);
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client = msi_irq->client;
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msi = client->msi;
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mutex_lock(&msi->mutex);
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bitmap_clear(msi->bitmap, msi_irq->pos, nr_irqs);
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client->nr_irqs -= nr_irqs;
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if (!client->nr_irqs) {
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if (msi->type == MSM_MSI_TYPE_QCOM)
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dma_unmap_resource(client->dev, client->msi_addr,
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PAGE_SIZE, DMA_FROM_DEVICE, 0);
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list_del(&client->node);
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devm_kfree(msi->dev, client);
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}
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mutex_unlock(&msi->mutex);
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.alloc = msm_msi_irq_domain_alloc,
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.free = msm_msi_irq_domain_free,
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};
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static int msm_msi_alloc_domains(struct msm_msi *msi)
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{
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msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_virqs,
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&msi_domain_ops, msi);
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if (!msi->inner_domain) {
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dev_err(msi->dev, "MSI: failed to create IRQ domain\n");
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return -ENOMEM;
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}
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msi->msi_domain = pci_msi_create_irq_domain(
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of_node_to_fwnode(msi->of_node),
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&msm_msi_domain_info,
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msi->inner_domain);
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if (!msi->msi_domain) {
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dev_err(msi->dev, "MSI: failed to create MSI domain\n");
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irq_domain_remove(msi->inner_domain);
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return -ENOMEM;
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}
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return 0;
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}
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|
|
static int msm_msi_snps_irq_setup(struct msm_msi *msi)
|
|
{
|
|
int i, index, ret;
|
|
struct msm_msi_grp *msi_grp;
|
|
struct msm_msi_irq *msi_irq;
|
|
unsigned int irq = 0;
|
|
|
|
/* setup each MSI group. nr_hwirqs == nr_grps */
|
|
for (i = 0; i < msi->nr_hwirqs; i++) {
|
|
irq = irq_of_parse_and_map(msi->of_node, i);
|
|
if (!irq) {
|
|
dev_err(msi->dev,
|
|
"MSI: failed to parse/map interrupt\n");
|
|
ret = -ENODEV;
|
|
goto free_irqs;
|
|
}
|
|
|
|
msi_grp = &msi->grps[i];
|
|
msi_grp->int_en_reg = msi->pcie_cfg +
|
|
PCIE_MSI_CTRL_INT_N_EN_OFFS(i);
|
|
msi_grp->int_mask_reg = msi->pcie_cfg +
|
|
PCIE_MSI_CTRL_INT_N_MASK_OFFS(i);
|
|
msi_grp->int_status_reg = msi->pcie_cfg +
|
|
PCIE_MSI_CTRL_INT_N_STATUS_OFFS(i);
|
|
|
|
for (index = 0; index < MSI_IRQ_PER_GRP; index++) {
|
|
msi_irq = &msi_grp->irqs[index];
|
|
|
|
msi_irq->grp = msi_grp;
|
|
msi_irq->grp_index = index;
|
|
msi_irq->pos = (i * MSI_IRQ_PER_GRP) + index;
|
|
msi_irq->hwirq = irq;
|
|
}
|
|
|
|
irq_set_chained_handler_and_data(irq, msm_msi_snps_handler,
|
|
msi_grp);
|
|
}
|
|
|
|
return 0;
|
|
|
|
free_irqs:
|
|
for (--i; i >= 0; i--) {
|
|
irq = msi->grps[i].irqs[0].hwirq;
|
|
|
|
irq_set_chained_handler_and_data(irq, NULL, NULL);
|
|
irq_dispose_mapping(irq);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int msm_msi_qgic_irq_setup(struct msm_msi *msi)
|
|
{
|
|
int i, ret;
|
|
u32 index, grp;
|
|
struct msm_msi_grp *msi_grp;
|
|
struct msm_msi_irq *msi_irq;
|
|
unsigned int irq = 0;
|
|
|
|
for (i = 0; i < msi->nr_hwirqs; i++) {
|
|
irq = irq_of_parse_and_map(msi->of_node, i);
|
|
if (!irq) {
|
|
dev_err(msi->dev,
|
|
"MSI: failed to parse/map interrupt\n");
|
|
ret = -ENODEV;
|
|
goto free_irqs;
|
|
}
|
|
|
|
grp = i / MSI_IRQ_PER_GRP;
|
|
index = i % MSI_IRQ_PER_GRP;
|
|
msi_grp = &msi->grps[grp];
|
|
msi_irq = &msi_grp->irqs[index];
|
|
|
|
msi_irq->grp = msi_grp;
|
|
msi_irq->grp_index = index;
|
|
msi_irq->pos = i;
|
|
msi_irq->hwirq = irq;
|
|
|
|
irq_set_chained_handler_and_data(irq, msm_msi_qgic_handler,
|
|
msi);
|
|
}
|
|
|
|
return 0;
|
|
|
|
free_irqs:
|
|
for (--i; i >= 0; i--) {
|
|
grp = i / MSI_IRQ_PER_GRP;
|
|
index = i % MSI_IRQ_PER_GRP;
|
|
irq = msi->grps[grp].irqs[index].hwirq;
|
|
|
|
irq_set_chained_handler_and_data(irq, NULL, NULL);
|
|
irq_dispose_mapping(irq);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* control access to PCIe MSI registers */
|
|
void msm_msi_config_access(struct irq_domain *domain, bool allow)
|
|
{
|
|
struct msm_msi *msi = domain->parent->host_data;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&msi->cfg_lock, flags);
|
|
msi->cfg_access = allow;
|
|
spin_unlock_irqrestore(&msi->cfg_lock, flags);
|
|
}
|
|
EXPORT_SYMBOL(msm_msi_config_access);
|
|
|
|
void msm_msi_config(struct irq_domain *domain)
|
|
{
|
|
struct msm_msi *msi;
|
|
int i;
|
|
|
|
msi = domain->parent->host_data;
|
|
|
|
/* PCIe core driver sets to false during LPM */
|
|
msm_msi_config_access(domain, true);
|
|
|
|
if (msi->type == MSM_MSI_TYPE_QCOM)
|
|
return;
|
|
|
|
/* program Synopsys MSI termination address */
|
|
writel_relaxed(msi->msi_addr, msi->pcie_cfg + PCIE_MSI_CTRL_ADDR_OFFS);
|
|
writel_relaxed(0, msi->pcie_cfg + PCIE_MSI_CTRL_UPPER_ADDR_OFFS);
|
|
|
|
/* restore mask and enable all interrupts for each group */
|
|
for (i = 0; i < msi->nr_grps; i++) {
|
|
struct msm_msi_grp *msi_grp = &msi->grps[i];
|
|
|
|
writel_relaxed(msi_grp->mask, msi_grp->int_mask_reg);
|
|
writel_relaxed(~0, msi_grp->int_en_reg);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(msm_msi_config);
|
|
|
|
int msm_msi_init(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct msm_msi *msi;
|
|
struct device_node *of_node;
|
|
const __be32 *prop_val;
|
|
struct resource *res;
|
|
int (*msi_irq_setup)(struct msm_msi *);
|
|
|
|
if (!dev->of_node) {
|
|
dev_err(dev, "MSI: missing DT node\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
of_node = of_parse_phandle(dev->of_node, "msi-parent", 0);
|
|
if (!of_node) {
|
|
dev_err(dev, "MSI: no phandle for MSI found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!of_device_is_compatible(of_node, "qcom,pci-msi")) {
|
|
dev_err(dev, "MSI: no compatible qcom,pci-msi found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!of_find_property(of_node, "msi-controller", NULL))
|
|
return -ENODEV;
|
|
|
|
msi = devm_kzalloc(dev, sizeof(*msi), GFP_KERNEL);
|
|
if (!msi)
|
|
return -ENOMEM;
|
|
|
|
msi->dev = dev;
|
|
msi->of_node = of_node;
|
|
mutex_init(&msi->mutex);
|
|
spin_lock_init(&msi->cfg_lock);
|
|
INIT_LIST_HEAD(&msi->clients);
|
|
|
|
prop_val = of_get_address(msi->of_node, 0, NULL, NULL);
|
|
if (!prop_val) {
|
|
dev_err(msi->dev, "MSI: missing 'reg' devicetree\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
msi->msi_addr = be32_to_cpup(prop_val);
|
|
if (!msi->msi_addr) {
|
|
dev_err(msi->dev, "MSI: failed to get MSI address\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
msi->type = of_property_read_bool(msi->of_node, "qcom,snps") ?
|
|
MSM_MSI_TYPE_SNPS : MSM_MSI_TYPE_QCOM;
|
|
dev_info(msi->dev, "MSI: %s controller is present\n",
|
|
msi->type == MSM_MSI_TYPE_SNPS ? "synopsys" : "qgic");
|
|
|
|
msi->nr_hwirqs = of_irq_count(msi->of_node);
|
|
if (!msi->nr_hwirqs) {
|
|
dev_err(msi->dev, "MSI: found no MSI interrupts\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (msi->type == MSM_MSI_TYPE_SNPS) {
|
|
res = platform_get_resource_byname(to_platform_device(dev),
|
|
IORESOURCE_MEM, "dm_core");
|
|
if (!res) {
|
|
dev_err(msi->dev,
|
|
"MSI: failed to get PCIe register base\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
msi->pcie_cfg = devm_ioremap(msi->dev, res->start,
|
|
resource_size(res));
|
|
if (!msi->pcie_cfg)
|
|
return -ENOMEM;
|
|
|
|
msi->nr_virqs = msi->nr_hwirqs * MSI_IRQ_PER_GRP;
|
|
msi->nr_grps = msi->nr_hwirqs;
|
|
msi->mask_irq = msm_msi_snps_mask_irq;
|
|
msi->unmask_irq = msm_msi_snps_unmask_irq;
|
|
msi_irq_setup = msm_msi_snps_irq_setup;
|
|
} else {
|
|
msi->nr_virqs = msi->nr_hwirqs;
|
|
msi->nr_grps = 1;
|
|
msi->mask_irq = msm_msi_qgic_mask_irq;
|
|
msi->unmask_irq = msm_msi_qgic_unmask_irq;
|
|
msi_irq_setup = msm_msi_qgic_irq_setup;
|
|
}
|
|
|
|
msi->grps = devm_kcalloc(msi->dev, msi->nr_grps,
|
|
sizeof(*msi->grps), GFP_KERNEL);
|
|
if (!msi->grps)
|
|
return -ENOMEM;
|
|
|
|
msi->bitmap = devm_kcalloc(msi->dev, BITS_TO_LONGS(msi->nr_virqs),
|
|
sizeof(*msi->bitmap), GFP_KERNEL);
|
|
if (!msi->bitmap)
|
|
return -ENOMEM;
|
|
|
|
ret = msm_msi_alloc_domains(msi);
|
|
if (ret) {
|
|
dev_err(msi->dev, "MSI: failed to allocate MSI domains\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = msi_irq_setup(msi);
|
|
if (ret)
|
|
goto remove_domains;
|
|
|
|
msm_msi_config(msi->msi_domain);
|
|
|
|
return 0;
|
|
|
|
remove_domains:
|
|
irq_domain_remove(msi->msi_domain);
|
|
irq_domain_remove(msi->inner_domain);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(msm_msi_init);
|
|
|