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817 lines
21 KiB
817 lines
21 KiB
/*
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* cxgb4_uld.c:Chelsio Upper Layer Driver Interface for T4/T5/T6 SGE management
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*
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* Copyright (c) 2016 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Written by: Atul Gupta (atul.gupta@chelsio.com)
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* Written by: Hariprasad Shenai (hariprasad@chelsio.com)
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/debugfs.h>
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#include <linux/export.h>
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#include <linux/list.h>
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#include <linux/skbuff.h>
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#include <linux/pci.h>
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#include "cxgb4.h"
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#include "cxgb4_uld.h"
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#include "t4_regs.h"
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#include "t4fw_api.h"
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#include "t4_msg.h"
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#define for_each_uldrxq(m, i) for (i = 0; i < ((m)->nrxq + (m)->nciq); i++)
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static int get_msix_idx_from_bmap(struct adapter *adap)
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{
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struct uld_msix_bmap *bmap = &adap->msix_bmap_ulds;
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unsigned long flags;
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unsigned int msix_idx;
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spin_lock_irqsave(&bmap->lock, flags);
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msix_idx = find_first_zero_bit(bmap->msix_bmap, bmap->mapsize);
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if (msix_idx < bmap->mapsize) {
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__set_bit(msix_idx, bmap->msix_bmap);
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} else {
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spin_unlock_irqrestore(&bmap->lock, flags);
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return -ENOSPC;
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}
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spin_unlock_irqrestore(&bmap->lock, flags);
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return msix_idx;
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}
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static void free_msix_idx_in_bmap(struct adapter *adap, unsigned int msix_idx)
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{
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struct uld_msix_bmap *bmap = &adap->msix_bmap_ulds;
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unsigned long flags;
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spin_lock_irqsave(&bmap->lock, flags);
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__clear_bit(msix_idx, bmap->msix_bmap);
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spin_unlock_irqrestore(&bmap->lock, flags);
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}
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/* Flush the aggregated lro sessions */
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static void uldrx_flush_handler(struct sge_rspq *q)
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{
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struct adapter *adap = q->adap;
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if (adap->uld[q->uld].lro_flush)
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adap->uld[q->uld].lro_flush(&q->lro_mgr);
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}
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/**
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* uldrx_handler - response queue handler for ULD queues
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* @q: the response queue that received the packet
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* @rsp: the response queue descriptor holding the offload message
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* @gl: the gather list of packet fragments
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*
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* Deliver an ingress offload packet to a ULD. All processing is done by
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* the ULD, we just maintain statistics.
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*/
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static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
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const struct pkt_gl *gl)
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{
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struct adapter *adap = q->adap;
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struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
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int ret;
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/* FW can send CPLs encapsulated in a CPL_FW4_MSG */
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if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
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((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
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rsp += 2;
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if (q->flush_handler)
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ret = adap->uld[q->uld].lro_rx_handler(adap->uld[q->uld].handle,
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rsp, gl, &q->lro_mgr,
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&q->napi);
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else
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ret = adap->uld[q->uld].rx_handler(adap->uld[q->uld].handle,
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rsp, gl);
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if (ret) {
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rxq->stats.nomem++;
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return -1;
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}
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if (!gl)
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rxq->stats.imm++;
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else if (gl == CXGB4_MSG_AN)
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rxq->stats.an++;
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else
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rxq->stats.pkts++;
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return 0;
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}
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static int alloc_uld_rxqs(struct adapter *adap,
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struct sge_uld_rxq_info *rxq_info, bool lro)
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{
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unsigned int nq = rxq_info->nrxq + rxq_info->nciq;
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int i, err, msi_idx, que_idx = 0, bmap_idx = 0;
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struct sge_ofld_rxq *q = rxq_info->uldrxq;
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unsigned short *ids = rxq_info->rspq_id;
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struct sge *s = &adap->sge;
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unsigned int per_chan;
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per_chan = rxq_info->nrxq / adap->params.nports;
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if (adap->flags & USING_MSIX)
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msi_idx = 1;
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else
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msi_idx = -((int)s->intrq.abs_id + 1);
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for (i = 0; i < nq; i++, q++) {
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if (i == rxq_info->nrxq) {
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/* start allocation of concentrator queues */
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per_chan = rxq_info->nciq / adap->params.nports;
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que_idx = 0;
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}
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if (msi_idx >= 0) {
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bmap_idx = get_msix_idx_from_bmap(adap);
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if (bmap_idx < 0) {
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err = -ENOSPC;
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goto freeout;
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}
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msi_idx = adap->msix_info_ulds[bmap_idx].idx;
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}
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err = t4_sge_alloc_rxq(adap, &q->rspq, false,
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adap->port[que_idx++ / per_chan],
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msi_idx,
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q->fl.size ? &q->fl : NULL,
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uldrx_handler,
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lro ? uldrx_flush_handler : NULL,
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0);
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if (err)
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goto freeout;
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if (msi_idx >= 0)
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rxq_info->msix_tbl[i] = bmap_idx;
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memset(&q->stats, 0, sizeof(q->stats));
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if (ids)
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ids[i] = q->rspq.abs_id;
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}
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return 0;
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freeout:
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q = rxq_info->uldrxq;
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for ( ; i; i--, q++) {
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if (q->rspq.desc)
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free_rspq_fl(adap, &q->rspq,
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q->fl.size ? &q->fl : NULL);
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}
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return err;
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}
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static int
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setup_sge_queues_uld(struct adapter *adap, unsigned int uld_type, bool lro)
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{
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struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
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int i, ret = 0;
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if (adap->flags & USING_MSIX) {
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rxq_info->msix_tbl = kcalloc((rxq_info->nrxq + rxq_info->nciq),
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sizeof(unsigned short),
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GFP_KERNEL);
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if (!rxq_info->msix_tbl)
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return -ENOMEM;
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}
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ret = !(!alloc_uld_rxqs(adap, rxq_info, lro));
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/* Tell uP to route control queue completions to rdma rspq */
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if (adap->flags & FULL_INIT_DONE &&
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!ret && uld_type == CXGB4_ULD_RDMA) {
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struct sge *s = &adap->sge;
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unsigned int cmplqid;
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u32 param, cmdop;
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cmdop = FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL;
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for_each_port(adap, i) {
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cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
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param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
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FW_PARAMS_PARAM_X_V(cmdop) |
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FW_PARAMS_PARAM_YZ_V(s->ctrlq[i].q.cntxt_id));
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ret = t4_set_params(adap, adap->mbox, adap->pf,
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0, 1, ¶m, &cmplqid);
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}
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}
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return ret;
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}
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static void t4_free_uld_rxqs(struct adapter *adap, int n,
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struct sge_ofld_rxq *q)
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{
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for ( ; n; n--, q++) {
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if (q->rspq.desc)
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free_rspq_fl(adap, &q->rspq,
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q->fl.size ? &q->fl : NULL);
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}
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}
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static void free_sge_queues_uld(struct adapter *adap, unsigned int uld_type)
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{
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struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
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if (adap->flags & FULL_INIT_DONE && uld_type == CXGB4_ULD_RDMA) {
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struct sge *s = &adap->sge;
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u32 param, cmdop, cmplqid = 0;
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int i;
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cmdop = FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL;
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for_each_port(adap, i) {
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param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
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FW_PARAMS_PARAM_X_V(cmdop) |
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FW_PARAMS_PARAM_YZ_V(s->ctrlq[i].q.cntxt_id));
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t4_set_params(adap, adap->mbox, adap->pf,
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0, 1, ¶m, &cmplqid);
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}
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}
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if (rxq_info->nciq)
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t4_free_uld_rxqs(adap, rxq_info->nciq,
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rxq_info->uldrxq + rxq_info->nrxq);
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t4_free_uld_rxqs(adap, rxq_info->nrxq, rxq_info->uldrxq);
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if (adap->flags & USING_MSIX)
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kfree(rxq_info->msix_tbl);
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}
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static int cfg_queues_uld(struct adapter *adap, unsigned int uld_type,
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const struct cxgb4_uld_info *uld_info)
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{
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struct sge *s = &adap->sge;
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struct sge_uld_rxq_info *rxq_info;
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int i, nrxq, ciq_size;
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rxq_info = kzalloc(sizeof(*rxq_info), GFP_KERNEL);
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if (!rxq_info)
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return -ENOMEM;
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if (adap->flags & USING_MSIX && uld_info->nrxq > s->nqs_per_uld) {
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i = s->nqs_per_uld;
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rxq_info->nrxq = roundup(i, adap->params.nports);
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} else {
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i = min_t(int, uld_info->nrxq,
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num_online_cpus());
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rxq_info->nrxq = roundup(i, adap->params.nports);
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}
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if (!uld_info->ciq) {
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rxq_info->nciq = 0;
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} else {
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if (adap->flags & USING_MSIX)
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rxq_info->nciq = min_t(int, s->nqs_per_uld,
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num_online_cpus());
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else
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rxq_info->nciq = min_t(int, MAX_OFLD_QSETS,
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num_online_cpus());
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rxq_info->nciq = ((rxq_info->nciq / adap->params.nports) *
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adap->params.nports);
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rxq_info->nciq = max_t(int, rxq_info->nciq,
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adap->params.nports);
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}
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nrxq = rxq_info->nrxq + rxq_info->nciq; /* total rxq's */
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rxq_info->uldrxq = kcalloc(nrxq, sizeof(struct sge_ofld_rxq),
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GFP_KERNEL);
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if (!rxq_info->uldrxq) {
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kfree(rxq_info);
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return -ENOMEM;
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}
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rxq_info->rspq_id = kcalloc(nrxq, sizeof(unsigned short), GFP_KERNEL);
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if (!rxq_info->rspq_id) {
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kfree(rxq_info->uldrxq);
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kfree(rxq_info);
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return -ENOMEM;
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}
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for (i = 0; i < rxq_info->nrxq; i++) {
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struct sge_ofld_rxq *r = &rxq_info->uldrxq[i];
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init_rspq(adap, &r->rspq, 5, 1, uld_info->rxq_size, 64);
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r->rspq.uld = uld_type;
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r->fl.size = 72;
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}
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ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
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if (ciq_size > SGE_MAX_IQ_SIZE) {
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dev_warn(adap->pdev_dev, "CIQ size too small for available IQs\n");
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ciq_size = SGE_MAX_IQ_SIZE;
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}
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for (i = rxq_info->nrxq; i < nrxq; i++) {
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struct sge_ofld_rxq *r = &rxq_info->uldrxq[i];
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init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
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r->rspq.uld = uld_type;
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}
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memcpy(rxq_info->name, uld_info->name, IFNAMSIZ);
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adap->sge.uld_rxq_info[uld_type] = rxq_info;
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return 0;
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}
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static void free_queues_uld(struct adapter *adap, unsigned int uld_type)
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{
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struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
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adap->sge.uld_rxq_info[uld_type] = NULL;
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kfree(rxq_info->rspq_id);
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kfree(rxq_info->uldrxq);
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kfree(rxq_info);
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}
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static int
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request_msix_queue_irqs_uld(struct adapter *adap, unsigned int uld_type)
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{
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struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
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int err = 0;
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unsigned int idx, bmap_idx;
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for_each_uldrxq(rxq_info, idx) {
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bmap_idx = rxq_info->msix_tbl[idx];
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err = request_irq(adap->msix_info_ulds[bmap_idx].vec,
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t4_sge_intr_msix, 0,
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adap->msix_info_ulds[bmap_idx].desc,
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&rxq_info->uldrxq[idx].rspq);
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if (err)
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goto unwind;
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}
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return 0;
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unwind:
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while (idx-- > 0) {
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bmap_idx = rxq_info->msix_tbl[idx];
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free_msix_idx_in_bmap(adap, bmap_idx);
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free_irq(adap->msix_info_ulds[bmap_idx].vec,
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&rxq_info->uldrxq[idx].rspq);
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}
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return err;
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}
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static void
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free_msix_queue_irqs_uld(struct adapter *adap, unsigned int uld_type)
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{
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struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
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unsigned int idx, bmap_idx;
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for_each_uldrxq(rxq_info, idx) {
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bmap_idx = rxq_info->msix_tbl[idx];
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free_msix_idx_in_bmap(adap, bmap_idx);
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free_irq(adap->msix_info_ulds[bmap_idx].vec,
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&rxq_info->uldrxq[idx].rspq);
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}
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}
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static void name_msix_vecs_uld(struct adapter *adap, unsigned int uld_type)
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{
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struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
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int n = sizeof(adap->msix_info_ulds[0].desc);
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unsigned int idx, bmap_idx;
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for_each_uldrxq(rxq_info, idx) {
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bmap_idx = rxq_info->msix_tbl[idx];
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snprintf(adap->msix_info_ulds[bmap_idx].desc, n, "%s-%s%d",
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adap->port[0]->name, rxq_info->name, idx);
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}
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}
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static void enable_rx(struct adapter *adap, struct sge_rspq *q)
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{
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if (!q)
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return;
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if (q->handler)
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napi_enable(&q->napi);
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/* 0-increment GTS to start the timer and enable interrupts */
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t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
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SEINTARM_V(q->intr_params) |
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INGRESSQID_V(q->cntxt_id));
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}
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static void quiesce_rx(struct adapter *adap, struct sge_rspq *q)
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{
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if (q && q->handler)
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napi_disable(&q->napi);
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}
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static void enable_rx_uld(struct adapter *adap, unsigned int uld_type)
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{
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struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
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int idx;
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for_each_uldrxq(rxq_info, idx)
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enable_rx(adap, &rxq_info->uldrxq[idx].rspq);
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}
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static void quiesce_rx_uld(struct adapter *adap, unsigned int uld_type)
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{
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struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
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int idx;
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for_each_uldrxq(rxq_info, idx)
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quiesce_rx(adap, &rxq_info->uldrxq[idx].rspq);
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}
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|
|
static void
|
|
free_sge_txq_uld(struct adapter *adap, struct sge_uld_txq_info *txq_info)
|
|
{
|
|
int nq = txq_info->ntxq;
|
|
int i;
|
|
|
|
for (i = 0; i < nq; i++) {
|
|
struct sge_uld_txq *txq = &txq_info->uldtxq[i];
|
|
|
|
if (txq && txq->q.desc) {
|
|
tasklet_kill(&txq->qresume_tsk);
|
|
t4_ofld_eq_free(adap, adap->mbox, adap->pf, 0,
|
|
txq->q.cntxt_id);
|
|
free_tx_desc(adap, &txq->q, txq->q.in_use, false);
|
|
kfree(txq->q.sdesc);
|
|
__skb_queue_purge(&txq->sendq);
|
|
free_txq(adap, &txq->q);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int
|
|
alloc_sge_txq_uld(struct adapter *adap, struct sge_uld_txq_info *txq_info,
|
|
unsigned int uld_type)
|
|
{
|
|
struct sge *s = &adap->sge;
|
|
int nq = txq_info->ntxq;
|
|
int i, j, err;
|
|
|
|
j = nq / adap->params.nports;
|
|
for (i = 0; i < nq; i++) {
|
|
struct sge_uld_txq *txq = &txq_info->uldtxq[i];
|
|
|
|
txq->q.size = 1024;
|
|
err = t4_sge_alloc_uld_txq(adap, txq, adap->port[i / j],
|
|
s->fw_evtq.cntxt_id, uld_type);
|
|
if (err)
|
|
goto freeout;
|
|
}
|
|
return 0;
|
|
freeout:
|
|
free_sge_txq_uld(adap, txq_info);
|
|
return err;
|
|
}
|
|
|
|
static void
|
|
release_sge_txq_uld(struct adapter *adap, unsigned int uld_type)
|
|
{
|
|
struct sge_uld_txq_info *txq_info = NULL;
|
|
int tx_uld_type = TX_ULD(uld_type);
|
|
|
|
txq_info = adap->sge.uld_txq_info[tx_uld_type];
|
|
|
|
if (txq_info && atomic_dec_and_test(&txq_info->users)) {
|
|
free_sge_txq_uld(adap, txq_info);
|
|
kfree(txq_info->uldtxq);
|
|
kfree(txq_info);
|
|
adap->sge.uld_txq_info[tx_uld_type] = NULL;
|
|
}
|
|
}
|
|
|
|
static int
|
|
setup_sge_txq_uld(struct adapter *adap, unsigned int uld_type,
|
|
const struct cxgb4_uld_info *uld_info)
|
|
{
|
|
struct sge_uld_txq_info *txq_info = NULL;
|
|
int tx_uld_type, i;
|
|
|
|
tx_uld_type = TX_ULD(uld_type);
|
|
txq_info = adap->sge.uld_txq_info[tx_uld_type];
|
|
|
|
if ((tx_uld_type == CXGB4_TX_OFLD) && txq_info &&
|
|
(atomic_inc_return(&txq_info->users) > 1))
|
|
return 0;
|
|
|
|
txq_info = kzalloc(sizeof(*txq_info), GFP_KERNEL);
|
|
if (!txq_info)
|
|
return -ENOMEM;
|
|
|
|
i = min_t(int, uld_info->ntxq, num_online_cpus());
|
|
txq_info->ntxq = roundup(i, adap->params.nports);
|
|
|
|
txq_info->uldtxq = kcalloc(txq_info->ntxq, sizeof(struct sge_uld_txq),
|
|
GFP_KERNEL);
|
|
if (!txq_info->uldtxq) {
|
|
kfree(txq_info);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (alloc_sge_txq_uld(adap, txq_info, tx_uld_type)) {
|
|
kfree(txq_info->uldtxq);
|
|
kfree(txq_info);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
atomic_inc(&txq_info->users);
|
|
adap->sge.uld_txq_info[tx_uld_type] = txq_info;
|
|
return 0;
|
|
}
|
|
|
|
static void uld_queue_init(struct adapter *adap, unsigned int uld_type,
|
|
struct cxgb4_lld_info *lli)
|
|
{
|
|
struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
|
|
|
|
lli->rxq_ids = rxq_info->rspq_id;
|
|
lli->nrxq = rxq_info->nrxq;
|
|
lli->ciq_ids = rxq_info->rspq_id + rxq_info->nrxq;
|
|
lli->nciq = rxq_info->nciq;
|
|
}
|
|
|
|
int t4_uld_mem_alloc(struct adapter *adap)
|
|
{
|
|
struct sge *s = &adap->sge;
|
|
|
|
adap->uld = kcalloc(CXGB4_ULD_MAX, sizeof(*adap->uld), GFP_KERNEL);
|
|
if (!adap->uld)
|
|
return -ENOMEM;
|
|
|
|
s->uld_rxq_info = kzalloc(CXGB4_ULD_MAX *
|
|
sizeof(struct sge_uld_rxq_info *),
|
|
GFP_KERNEL);
|
|
if (!s->uld_rxq_info)
|
|
goto err_uld;
|
|
|
|
s->uld_txq_info = kzalloc(CXGB4_TX_MAX *
|
|
sizeof(struct sge_uld_txq_info *),
|
|
GFP_KERNEL);
|
|
if (!s->uld_txq_info)
|
|
goto err_uld_rx;
|
|
return 0;
|
|
|
|
err_uld_rx:
|
|
kfree(s->uld_rxq_info);
|
|
err_uld:
|
|
kfree(adap->uld);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
void t4_uld_mem_free(struct adapter *adap)
|
|
{
|
|
struct sge *s = &adap->sge;
|
|
|
|
kfree(s->uld_txq_info);
|
|
kfree(s->uld_rxq_info);
|
|
kfree(adap->uld);
|
|
}
|
|
|
|
/* This function should be called with uld_mutex taken. */
|
|
static void cxgb4_shutdown_uld_adapter(struct adapter *adap, enum cxgb4_uld type)
|
|
{
|
|
if (adap->uld[type].handle) {
|
|
adap->uld[type].handle = NULL;
|
|
adap->uld[type].add = NULL;
|
|
release_sge_txq_uld(adap, type);
|
|
|
|
if (adap->flags & FULL_INIT_DONE)
|
|
quiesce_rx_uld(adap, type);
|
|
|
|
if (adap->flags & USING_MSIX)
|
|
free_msix_queue_irqs_uld(adap, type);
|
|
|
|
free_sge_queues_uld(adap, type);
|
|
free_queues_uld(adap, type);
|
|
}
|
|
}
|
|
|
|
void t4_uld_clean_up(struct adapter *adap)
|
|
{
|
|
unsigned int i;
|
|
|
|
mutex_lock(&uld_mutex);
|
|
for (i = 0; i < CXGB4_ULD_MAX; i++) {
|
|
if (!adap->uld[i].handle)
|
|
continue;
|
|
|
|
cxgb4_shutdown_uld_adapter(adap, i);
|
|
}
|
|
mutex_unlock(&uld_mutex);
|
|
}
|
|
|
|
static void uld_init(struct adapter *adap, struct cxgb4_lld_info *lld)
|
|
{
|
|
int i;
|
|
|
|
lld->pdev = adap->pdev;
|
|
lld->pf = adap->pf;
|
|
lld->l2t = adap->l2t;
|
|
lld->tids = &adap->tids;
|
|
lld->ports = adap->port;
|
|
lld->vr = &adap->vres;
|
|
lld->mtus = adap->params.mtus;
|
|
lld->ntxq = adap->sge.ofldqsets;
|
|
lld->nchan = adap->params.nports;
|
|
lld->nports = adap->params.nports;
|
|
lld->wr_cred = adap->params.ofldq_wr_cred;
|
|
lld->iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
|
|
lld->iscsi_tagmask = t4_read_reg(adap, ULP_RX_ISCSI_TAGMASK_A);
|
|
lld->iscsi_pgsz_order = t4_read_reg(adap, ULP_RX_ISCSI_PSZ_A);
|
|
lld->iscsi_llimit = t4_read_reg(adap, ULP_RX_ISCSI_LLIMIT_A);
|
|
lld->iscsi_ppm = &adap->iscsi_ppm;
|
|
lld->adapter_type = adap->params.chip;
|
|
lld->cclk_ps = 1000000000 / adap->params.vpd.cclk;
|
|
lld->udb_density = 1 << adap->params.sge.eq_qpp;
|
|
lld->ucq_density = 1 << adap->params.sge.iq_qpp;
|
|
lld->filt_mode = adap->params.tp.vlan_pri_map;
|
|
/* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
|
|
for (i = 0; i < NCHAN; i++)
|
|
lld->tx_modq[i] = i;
|
|
lld->gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
|
|
lld->db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
|
|
lld->fw_vers = adap->params.fw_vers;
|
|
lld->dbfifo_int_thresh = dbfifo_int_thresh;
|
|
lld->sge_ingpadboundary = adap->sge.fl_align;
|
|
lld->sge_egrstatuspagesize = adap->sge.stat_len;
|
|
lld->sge_pktshift = adap->sge.pktshift;
|
|
lld->ulp_crypto = adap->params.crypto;
|
|
lld->enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
|
|
lld->max_ordird_qp = adap->params.max_ordird_qp;
|
|
lld->max_ird_adapter = adap->params.max_ird_adapter;
|
|
lld->ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
|
|
lld->nodeid = dev_to_node(adap->pdev_dev);
|
|
lld->fr_nsmr_tpte_wr_support = adap->params.fr_nsmr_tpte_wr_support;
|
|
}
|
|
|
|
static int uld_attach(struct adapter *adap, unsigned int uld)
|
|
{
|
|
struct cxgb4_lld_info lli;
|
|
void *handle;
|
|
|
|
uld_init(adap, &lli);
|
|
uld_queue_init(adap, uld, &lli);
|
|
|
|
handle = adap->uld[uld].add(&lli);
|
|
if (IS_ERR(handle)) {
|
|
dev_warn(adap->pdev_dev,
|
|
"could not attach to the %s driver, error %ld\n",
|
|
adap->uld[uld].name, PTR_ERR(handle));
|
|
return PTR_ERR(handle);
|
|
}
|
|
|
|
adap->uld[uld].handle = handle;
|
|
t4_register_netevent_notifier();
|
|
|
|
if (adap->flags & FULL_INIT_DONE)
|
|
adap->uld[uld].state_change(handle, CXGB4_STATE_UP);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* cxgb4_register_uld - register an upper-layer driver
|
|
* @type: the ULD type
|
|
* @p: the ULD methods
|
|
*
|
|
* Registers an upper-layer driver with this driver and notifies the ULD
|
|
* about any presently available devices that support its type. Returns
|
|
* %-EBUSY if a ULD of the same type is already registered.
|
|
*/
|
|
int cxgb4_register_uld(enum cxgb4_uld type,
|
|
const struct cxgb4_uld_info *p)
|
|
{
|
|
unsigned int adap_idx = 0;
|
|
struct adapter *adap;
|
|
int ret = 0;
|
|
|
|
if (type >= CXGB4_ULD_MAX)
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&uld_mutex);
|
|
list_for_each_entry(adap, &adapter_list, list_node) {
|
|
if ((type == CXGB4_ULD_CRYPTO && !is_pci_uld(adap)) ||
|
|
(type != CXGB4_ULD_CRYPTO && !is_offload(adap)))
|
|
continue;
|
|
if (type == CXGB4_ULD_ISCSIT && is_t4(adap->params.chip))
|
|
continue;
|
|
ret = cfg_queues_uld(adap, type, p);
|
|
if (ret)
|
|
goto out;
|
|
ret = setup_sge_queues_uld(adap, type, p->lro);
|
|
if (ret)
|
|
goto free_queues;
|
|
if (adap->flags & USING_MSIX) {
|
|
name_msix_vecs_uld(adap, type);
|
|
ret = request_msix_queue_irqs_uld(adap, type);
|
|
if (ret)
|
|
goto free_rxq;
|
|
}
|
|
if (adap->flags & FULL_INIT_DONE)
|
|
enable_rx_uld(adap, type);
|
|
if (adap->uld[type].add) {
|
|
ret = -EBUSY;
|
|
goto free_irq;
|
|
}
|
|
ret = setup_sge_txq_uld(adap, type, p);
|
|
if (ret)
|
|
goto free_irq;
|
|
adap->uld[type] = *p;
|
|
ret = uld_attach(adap, type);
|
|
if (ret)
|
|
goto free_txq;
|
|
adap_idx++;
|
|
}
|
|
mutex_unlock(&uld_mutex);
|
|
return 0;
|
|
|
|
free_txq:
|
|
release_sge_txq_uld(adap, type);
|
|
free_irq:
|
|
if (adap->flags & FULL_INIT_DONE)
|
|
quiesce_rx_uld(adap, type);
|
|
if (adap->flags & USING_MSIX)
|
|
free_msix_queue_irqs_uld(adap, type);
|
|
free_rxq:
|
|
free_sge_queues_uld(adap, type);
|
|
free_queues:
|
|
free_queues_uld(adap, type);
|
|
out:
|
|
|
|
list_for_each_entry(adap, &adapter_list, list_node) {
|
|
if ((type == CXGB4_ULD_CRYPTO && !is_pci_uld(adap)) ||
|
|
(type != CXGB4_ULD_CRYPTO && !is_offload(adap)))
|
|
continue;
|
|
if (type == CXGB4_ULD_ISCSIT && is_t4(adap->params.chip))
|
|
continue;
|
|
if (!adap_idx)
|
|
break;
|
|
adap->uld[type].handle = NULL;
|
|
adap->uld[type].add = NULL;
|
|
release_sge_txq_uld(adap, type);
|
|
if (adap->flags & FULL_INIT_DONE)
|
|
quiesce_rx_uld(adap, type);
|
|
if (adap->flags & USING_MSIX)
|
|
free_msix_queue_irqs_uld(adap, type);
|
|
free_sge_queues_uld(adap, type);
|
|
free_queues_uld(adap, type);
|
|
adap_idx--;
|
|
}
|
|
mutex_unlock(&uld_mutex);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(cxgb4_register_uld);
|
|
|
|
/**
|
|
* cxgb4_unregister_uld - unregister an upper-layer driver
|
|
* @type: the ULD type
|
|
*
|
|
* Unregisters an existing upper-layer driver.
|
|
*/
|
|
int cxgb4_unregister_uld(enum cxgb4_uld type)
|
|
{
|
|
struct adapter *adap;
|
|
|
|
if (type >= CXGB4_ULD_MAX)
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&uld_mutex);
|
|
list_for_each_entry(adap, &adapter_list, list_node) {
|
|
if ((type == CXGB4_ULD_CRYPTO && !is_pci_uld(adap)) ||
|
|
(type != CXGB4_ULD_CRYPTO && !is_offload(adap)))
|
|
continue;
|
|
if (type == CXGB4_ULD_ISCSIT && is_t4(adap->params.chip))
|
|
continue;
|
|
|
|
cxgb4_shutdown_uld_adapter(adap, type);
|
|
}
|
|
mutex_unlock(&uld_mutex);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(cxgb4_unregister_uld);
|
|
|