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356 lines
9.0 KiB
356 lines
9.0 KiB
/* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef LINUX_MMC_CQ_HCI_H
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#define LINUX_MMC_CQ_HCI_H
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#include <linux/mmc/core.h>
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#include <linux/platform_device.h>
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#include <linux/keyslot-manager.h>
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/* registers */
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/* version */
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#define CQVER 0x00
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/* capabilities */
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#define CQCAP 0x04
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#define CQ_CAP_CS (1 << 28)
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#define CQ_CCAP 0x100
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#define CQ_CRYPTOCAP 0x104
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/* configuration */
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#define CQCFG 0x08
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#define CQ_DCMD 0x00001000
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#define CQ_TASK_DESC_SZ 0x00000100
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#define CQ_ENABLE 0x00000001
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#define CQ_ICE_ENABLE 0x00000002
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/* control */
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#define CQCTL 0x0C
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#define CLEAR_ALL_TASKS 0x00000100
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#define HALT 0x00000001
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/* interrupt status */
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#define CQIS 0x10
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#define CQIS_HAC (1 << 0)
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#define CQIS_TCC (1 << 1)
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#define CQIS_RED (1 << 2)
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#define CQIS_TCL (1 << 3)
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#define CQIS_GCE (1 << 4)
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#define CQIS_ICCE (1 << 5)
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/* interrupt status enable */
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#define CQISTE 0x14
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/* interrupt signal enable */
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#define CQISGE 0x18
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/* interrupt coalescing */
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#define CQIC 0x1C
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#define CQIC_ENABLE (1 << 31)
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#define CQIC_RESET (1 << 16)
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#define CQIC_ICCTHWEN (1 << 15)
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#define CQIC_ICCTH(x) ((x & 0x1F) << 8)
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#define CQIC_ICTOVALWEN (1 << 7)
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#define CQIC_ICTOVAL(x) (x & 0x7F)
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/* task list base address */
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#define CQTDLBA 0x20
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/* task list base address upper */
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#define CQTDLBAU 0x24
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/* door-bell */
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#define CQTDBR 0x28
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/* task completion notification */
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#define CQTCN 0x2C
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/* device queue status */
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#define CQDQS 0x30
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/* device pending tasks */
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#define CQDPT 0x34
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/* task clear */
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#define CQTCLR 0x38
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/* send status config 1 */
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#define CQSSC1 0x40
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/*
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* Value n means CQE would send CMD13 during the transfer of data block
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* BLOCK_CNT-n
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*/
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#define SEND_QSR_INTERVAL 0x70001
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/* send status config 2 */
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#define CQSSC2 0x44
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/* response for dcmd */
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#define CQCRDCT 0x48
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/* response mode error mask */
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#define CQRMEM 0x50
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#define CQ_EXCEPTION (1 << 6)
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/* write protection violation */
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#define WP_ERASE_SKIP (1 << 15)
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#define WP_VIOLATION (1 << 26)
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/* task error info */
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#define CQTERRI 0x54
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/* CQTERRI bit fields */
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#define CQ_RMECI 0x3F
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#define CQ_RMETI (0x1F << 8)
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#define CQ_RMEFV (1 << 15)
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#define CQ_DTECI (0x3F << 16)
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#define CQ_DTETI (0x1F << 24)
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#define CQ_DTEFV (1 << 31)
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#define GET_CMD_ERR_IDX(__r__) (__r__ & CQ_RMECI)
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#define GET_CMD_ERR_TAG(__r__) ((__r__ & CQ_RMETI) >> 8)
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#define GET_DAT_ERR_IDX(__r__) ((__r__ & CQ_DTECI) >> 16)
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#define GET_DAT_ERR_TAG(__r__) ((__r__ & CQ_DTETI) >> 24)
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/* command response index */
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#define CQCRI 0x58
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/* command response argument */
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#define CQCRA 0x5C
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#define CQ_INT_ALL 0x3F
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#define CQIC_DEFAULT_ICCTH 31
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#define CQIC_DEFAULT_ICTOVAL 1
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/* attribute fields */
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#define VALID(x) ((x & 1) << 0)
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#define END(x) ((x & 1) << 1)
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#define INT(x) ((x & 1) << 2)
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#define ACT(x) ((x & 0x7) << 3)
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/* data command task descriptor fields */
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#define FORCED_PROG(x) ((x & 1) << 6)
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#define CONTEXT(x) ((x & 0xF) << 7)
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#define DATA_TAG(x) ((x & 1) << 11)
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#define DATA_DIR(x) ((x & 1) << 12)
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#define PRIORITY(x) ((x & 1) << 13)
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#define QBAR(x) ((x & 1) << 14)
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#define REL_WRITE(x) ((x & 1) << 15)
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#define BLK_COUNT(x) ((x & 0xFFFF) << 16)
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#define BLK_ADDR(x) ((x & 0xFFFFFFFF) << 32)
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/* direct command task descriptor fields */
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#define CMD_INDEX(x) ((x & 0x3F) << 16)
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#define CMD_TIMING(x) ((x & 1) << 22)
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#define RESP_TYPE(x) ((x & 0x3) << 23)
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/* transfer descriptor fields */
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#define DAT_LENGTH(x) ((x & 0xFFFF) << 16)
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#define DAT_ADDR_LO(x) ((x & 0xFFFFFFFF) << 32)
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#define DAT_ADDR_HI(x) ((x & 0xFFFFFFFF) << 0)
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#define DATA_UNIT_NUM(x) (((u64)(x) & 0xFFFFFFFF) << 0)
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#define CRYPTO_CONFIG_INDEX(x) (((u64)(x) & 0xFF) << 32)
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#define CRYPTO_ENABLE(x) (((u64)(x) & 0x1) << 47)
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/* ICE context is present in the upper 64bits of task descriptor */
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#define CQ_TASK_DESC_ICE_PARAM_OFFSET 8
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/* ICE descriptor size */
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#define CQ_TASK_DESC_ICE_PARAMS_SIZE 8
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/*
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* Add new macro for updated CQ vendor specific
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* register address for SDHC v5.0 onwards.
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*/
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#define CQ_V5_VENDOR_CFG 0x900
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#define CQ_VENDOR_CFG 0x100
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#define CMDQ_SEND_STATUS_TRIGGER (1 << 31)
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struct cmdq_host;
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/* CCAP - Crypto Capability 100h */
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union cmdq_crypto_capabilities {
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__le32 reg_val;
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struct {
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u8 num_crypto_cap;
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u8 config_count;
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u8 reserved;
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u8 config_array_ptr;
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};
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};
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enum cmdq_crypto_key_size {
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CMDQ_CRYPTO_KEY_SIZE_INVALID = 0x0,
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CMDQ_CRYPTO_KEY_SIZE_128 = 0x1,
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CMDQ_CRYPTO_KEY_SIZE_192 = 0x2,
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CMDQ_CRYPTO_KEY_SIZE_256 = 0x3,
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CMDQ_CRYPTO_KEY_SIZE_512 = 0x4,
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};
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enum cmdq_crypto_alg {
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CMDQ_CRYPTO_ALG_AES_XTS = 0x0,
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CMDQ_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
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CMDQ_CRYPTO_ALG_AES_ECB = 0x2,
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CMDQ_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
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};
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/* x-CRYPTOCAP - Crypto Capability X */
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union cmdq_crypto_cap_entry {
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__le32 reg_val;
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struct {
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u8 algorithm_id;
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u8 sdus_mask; /* Supported data unit size mask */
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u8 key_size;
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u8 reserved;
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};
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};
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#define CMDQ_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
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#define CMDQ_CRYPTO_KEY_MAX_SIZE 64
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/* x-CRYPTOCFG - Crypto Configuration X */
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union cmdq_crypto_cfg_entry {
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__le32 reg_val[32];
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struct {
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u8 crypto_key[CMDQ_CRYPTO_KEY_MAX_SIZE];
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u8 data_unit_size;
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u8 crypto_cap_idx;
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u8 reserved_1;
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u8 config_enable;
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u8 reserved_multi_host;
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u8 reserved_2;
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u8 vsb[2];
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u8 reserved_3[56];
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};
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};
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struct cmdq_host_crypto_variant_ops {
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void (*setup_rq_keyslot_manager)(struct cmdq_host *host,
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struct request_queue *q);
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void (*destroy_rq_keyslot_manager)(struct cmdq_host *host,
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struct request_queue *q);
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#ifdef CONFIG_BLK_INLINE_ENCRYPTION
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int (*host_init_crypto)(struct cmdq_host *host,
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const struct keyslot_mgmt_ll_ops *ksm_ops);
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#endif
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void (*enable)(struct cmdq_host *host);
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void (*disable)(struct cmdq_host *host);
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int (*suspend)(struct cmdq_host *host);
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int (*resume)(struct cmdq_host *host);
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int (*debug)(struct cmdq_host *host);
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int (*prepare_crypto_desc)(struct cmdq_host *host,
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struct mmc_request *mrq, u64 *ice_ctx);
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int (*complete_crypto_desc)(struct cmdq_host *host,
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struct mmc_request *mrq, u64 *ice_ctx);
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int (*reset)(struct cmdq_host *host);
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int (*recovery_finish)(struct cmdq_host *host);
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int (*program_key)(struct cmdq_host *host,
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const union cmdq_crypto_cfg_entry *cfg, int slot);
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void *priv;
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};
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struct task_history {
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u64 task;
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bool is_dcmd;
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u32 tag;
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ktime_t issue_time;
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};
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struct cmdq_host {
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const struct cmdq_host_ops *ops;
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void __iomem *mmio;
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void __iomem *icemmio;
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struct mmc_host *mmc;
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/* 64 bit DMA */
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bool dma64;
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int num_slots;
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u32 dcmd_slot;
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u32 caps;
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#define CMDQ_TASK_DESC_SZ_128 0x1
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#define CMDQ_CAP_CRYPTO_SUPPORT 0x2
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u32 quirks;
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#define CMDQ_QUIRK_SHORT_TXFR_DESC_SZ 0x1
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#define CMDQ_QUIRK_NO_DCMD 0x2
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bool enabled;
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bool halted;
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bool init_done;
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bool offset_changed;
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u8 *desc_base;
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/* total descriptor size */
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u8 slot_sz;
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/* 64/128 bit depends on CQCFG */
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u8 task_desc_len;
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/* 64 bit on 32-bit arch, 128 bit on 64-bit */
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u8 link_desc_len;
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u8 *trans_desc_base;
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/* same length as transfer descriptor */
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u8 trans_desc_len;
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dma_addr_t desc_dma_base;
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dma_addr_t trans_desc_dma_base;
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struct task_history *thist;
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u8 thist_idx;
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struct completion halt_comp;
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struct mmc_request **mrq_slot;
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void *private;
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const struct cmdq_host_crypto_variant_ops *crypto_vops;
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#ifdef CONFIG_MMC_CQ_HCI_CRYPTO
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union cmdq_crypto_capabilities crypto_capabilities;
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union cmdq_crypto_cap_entry *crypto_cap_array;
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u32 crypto_cfg_register;
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#ifdef CONFIG_BLK_INLINE_ENCRYPTION
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struct keyslot_manager *ksm;
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#endif /* CONFIG_BLK_INLINE_ENCRYPTION */
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#endif /* CONFIG_SCSI_CQHCI_CRYPTO */
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};
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struct cmdq_host_ops {
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void (*set_transfer_params)(struct mmc_host *mmc);
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void (*set_data_timeout)(struct mmc_host *mmc, u32 val);
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void (*clear_set_irqs)(struct mmc_host *mmc, bool clear);
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void (*set_block_size)(struct mmc_host *mmc);
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void (*dump_vendor_regs)(struct mmc_host *mmc);
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void (*write_l)(struct cmdq_host *host, u32 val, int reg);
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u32 (*read_l)(struct cmdq_host *host, int reg);
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void (*clear_set_dumpregs)(struct mmc_host *mmc, bool set);
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void (*enhanced_strobe_mask)(struct mmc_host *mmc, bool set);
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int (*reset)(struct mmc_host *mmc);
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void (*post_cqe_halt)(struct mmc_host *mmc);
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};
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static inline void cmdq_writel(struct cmdq_host *host, u32 val, int reg)
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{
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if (unlikely(host->ops && host->ops->write_l))
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host->ops->write_l(host, val, reg);
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else
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writel_relaxed(val, host->mmio + reg);
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}
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static inline u32 cmdq_readl(struct cmdq_host *host, int reg)
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{
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if (unlikely(host->ops && host->ops->read_l))
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return host->ops->read_l(host, reg);
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else
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return readl_relaxed(host->mmio + reg);
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}
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extern irqreturn_t cmdq_irq(struct mmc_host *mmc, int err);
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extern int cmdq_init(struct cmdq_host *cq_host, struct mmc_host *mmc,
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bool dma64);
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extern struct cmdq_host *cmdq_pltfm_init(struct platform_device *pdev);
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#endif
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