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148 lines
4.8 KiB
148 lines
4.8 KiB
/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define ARM_SMMU_TESTBUS_SEL 0x25E4
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#define ARM_SMMU_TESTBUS 0x25E8
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#define ARM_SMMU_TESTBUS_SEL_HLOS1_NS 0x8
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#define DEBUG_TESTBUS_SEL_TBU 0x50
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#define DEBUG_TESTBUS_TBU 0x58
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#define CLIENT_DEBUG_SR_HALT_ACK 0x24
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#define TCU_PTW_TESTBUS (0x1 << 8)
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#define TCU_CACHE_TESTBUS ~TCU_PTW_TESTBUS
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#define TCU_PTW_TESTBUS_SEL (0x1 << 1)
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#define TCU_PTW_INTERNAL_STATES 3
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#define TCU_PTW_TESTBUS_SEL2 3
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#define TCU_PTW_QUEUE_START 32
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#define TCU_PTW_QUEUE_SIZE 32
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#define TCU_CACHE_TESTBUS_SEL 0x1
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#define TCU_CACHE_LOOKUP_QUEUE_SIZE 32
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#define TCU_CLK_TESTBUS_SEL 0x200
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#define TBU_CLK_GATE_CONTROLLER_TESTBUS_SEL 0x1
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#define TBU_QNS4_A2Q_TESTBUS_SEL (0x1 << 1)
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#define TBU_QNS4_Q2A_TESTBUS_SEL (0x1 << 2)
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#define TBU_MULTIMASTER_QCHANNEL_TESTBUS_SEL (0x1 << 3)
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#define TBU_CLK_GATE_CONTROLLER_TESTBUS (0x1 << 6)
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#define TBU_QNS4_A2Q_TESTBUS (0x2 << 6)
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#define TBU_QNS4_Q2A_TESTBUS (0x5 << 5)
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#define TBU_MULTIMASTER_QCHANNEL_TESTBUS (0x3 << 6)
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#define TBU_QNS4_BRIDGE_SIZE 32
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enum tcu_testbus {
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PTW_AND_CACHE_TESTBUS,
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CLK_TESTBUS,
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};
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enum testbus_sel {
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SEL_TCU,
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SEL_TBU,
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};
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enum testbus_ops {
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TESTBUS_SELECT,
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TESTBUS_OUTPUT,
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};
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#define ARM_SMMU_TNX_TCR_CNTL 0x130
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#define ARM_SMMU_CAPTURE1_MASK(i) (0x100 + (0x8)*(i-1))
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#define ARM_SMMU_CAPTURE1_MATCH(i) (0x118 + (0x8)*(i-1))
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#define ARM_SMMU_CAPTURE_SNAPSHOT(i, j) ((0x138 + (0x10)*i) + j*0x8)
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#define APPS_SMMU_TNX_TCR_CNTL_2 0x178
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#define NO_OF_MASK_AND_MATCH 0x3
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#define NO_OF_CAPTURE_POINTS 0x4
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#define REGS_PER_CAPTURE_POINT 0x2
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#define INTR_CLR (1 << 0)
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#define RESET_VALID (1 << 7)
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#ifdef CONFIG_ARM_SMMU
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u32 arm_smmu_debug_tbu_testbus_select(void __iomem *tbu_base,
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void __iomem *tcu_base, u32 testbus_version,
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bool write, u32 reg);
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u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base,
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u32 testbus_version);
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u32 arm_smmu_debug_tcu_testbus_select(void __iomem *base,
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void __iomem *tcu_base, enum tcu_testbus testbus,
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bool write, u32 val);
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u32 arm_smmu_debug_tcu_testbus_output(void __iomem *base);
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void arm_smmu_debug_dump_tbu_testbus(struct device *dev, void __iomem *tbu_base,
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void __iomem *tcu_base, int tbu_testbus_sel,
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u32 testbus_version);
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void arm_smmu_debug_dump_tcu_testbus(struct device *dev, void __iomem *base,
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void __iomem *tcu_base, int tcu_testbus_sel);
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void arm_smmu_debug_set_tnx_tcr_cntl(void __iomem *tbu_base, u64 val);
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unsigned long arm_smmu_debug_get_tnx_tcr_cntl(void __iomem *tbu_base);
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unsigned long arm_smmu_debug_get_tnx_tcr_cntl_2(void __iomem *tbu_base);
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void arm_smmu_debug_set_mask_and_match(void __iomem *tbu_base, u64 sel,
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u64 mask, u64 match);
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void arm_smmu_debug_get_mask_and_match(void __iomem *tbu_base,
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u64 *mask, u64 *match);
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void arm_smmu_debug_get_capture_snapshot(void __iomem *tbu_base,
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u64 snapshot[NO_OF_CAPTURE_POINTS][REGS_PER_CAPTURE_POINT]);
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void arm_smmu_debug_clear_intr_and_validbits(void __iomem *tbu_base);
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#else
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static inline u32 arm_smmu_debug_tbu_testbus_select(void __iomem *tbu_base,
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void __iomem *tcu_base, u32 testbus_version, bool write,
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u32 val)
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{
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}
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static inline u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base,
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u32 testbus_version)
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{
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}
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u32 arm_smmu_debug_tcu_testbus_select(void __iomem *base,
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void __iomem *tcu_base, enum tcu_testbus testbus,
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bool write, u32 val)
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{
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}
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static inline u32 arm_smmu_debug_tcu_testbus_output(void __iomem *base)
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{
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}
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static inline void arm_smmu_debug_dump_tbu_testbus(struct device *dev,
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void __iomem *tbu_base, void __iomem *tcu_base,
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int tbu_testbus_sel, u32 testbus_version)
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{
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}
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static inline void arm_smmu_debug_dump_tcu_testbus(struct device *dev,
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void __iomem *base, void __iomem *tcu_base,
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int tcu_testbus_sel)
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{
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}
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void arm_smmu_debug_set_tnx_tcr_cntl(void __iomem *tbu_base, u64 val)
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{
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}
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unsigned long arm_smmu_debug_get_tnx_tcr_cntl(void __iomem *tbu_base)
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{
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}
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unsigned long arm_smmu_debug_get_tnx_tcr_cntl_2(void __iomem *tbu_base)
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{
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}
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void arm_smmu_debug_set_mask_and_match(void __iomem *tbu_base, u64 sel,
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u64 mask, u64 match)
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{
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}
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void arm_smmu_debug_get_mask_and_match(void __iomem *tbu_base,
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u64 *mask, u64 *match)
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{
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}
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void arm_smmu_debug_get_capture_snapshot(void __iomem *tbu_base,
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u64 snapshot[NO_OF_CAPTURE_POINTS][REGS_PER_CAPTURE_POINT])
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{
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}
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void arm_smmu_debug_clear_intr_and_validbits(void __iomem *tbu_base)
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{
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}
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#endif
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