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290 lines
8.4 KiB
290 lines
8.4 KiB
/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include "arm-smmu-regs.h"
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#include "arm-smmu-debug.h"
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u32 arm_smmu_debug_tbu_testbus_select(void __iomem *tbu_base,
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void __iomem *tcu_base, u32 testbus_version,
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bool write, u32 val)
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{
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void __iomem *base;
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int offset;
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if (testbus_version == 1) {
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base = tcu_base;
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offset = ARM_SMMU_TESTBUS_SEL_HLOS1_NS;
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} else {
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base = tbu_base;
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offset = DEBUG_TESTBUS_SEL_TBU;
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}
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if (write) {
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writel_relaxed(val, base + offset);
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/* Make sure tbu select register is written to */
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wmb();
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} else {
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return readl_relaxed(base + offset);
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}
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return 0;
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}
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u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base,
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u32 testbus_version)
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{
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int offset = (testbus_version == 1) ?
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CLIENT_DEBUG_SR_HALT_ACK : DEBUG_TESTBUS_TBU;
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return readl_relaxed(tbu_base + offset);
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}
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u32 arm_smmu_debug_tcu_testbus_select(void __iomem *base,
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void __iomem *tcu_base, enum tcu_testbus testbus,
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bool write, u32 val)
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{
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int offset;
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if (testbus == CLK_TESTBUS) {
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base = tcu_base;
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offset = ARM_SMMU_TESTBUS_SEL_HLOS1_NS;
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} else {
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offset = ARM_SMMU_TESTBUS_SEL;
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}
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if (write) {
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writel_relaxed(val, base + offset);
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/* Make sure tcu select register is written to */
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wmb();
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} else {
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return readl_relaxed(base + offset);
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}
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return 0;
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}
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u32 arm_smmu_debug_tcu_testbus_output(void __iomem *base)
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{
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return readl_relaxed(base + ARM_SMMU_TESTBUS);
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}
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static void arm_smmu_debug_dump_tbu_qns4_testbus(struct device *dev,
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void __iomem *tbu_base, void __iomem *tcu_base,
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u32 testbus_version)
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{
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int i;
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u32 reg;
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for (i = 0 ; i < TBU_QNS4_BRIDGE_SIZE; ++i) {
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reg = arm_smmu_debug_tbu_testbus_select(tbu_base, tcu_base,
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testbus_version, READ, 0);
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reg = (reg & ~GENMASK(4, 0)) | i << 0;
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arm_smmu_debug_tbu_testbus_select(tbu_base, tcu_base,
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testbus_version, WRITE, reg);
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dev_info(dev, "testbus_sel: 0x%x Index: %d val: 0x%x\n",
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arm_smmu_debug_tbu_testbus_select(tbu_base, tcu_base,
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testbus_version, READ, 0), i,
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arm_smmu_debug_tbu_testbus_output(tbu_base,
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testbus_version));
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}
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}
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static void arm_smmu_debug_program_tbu_testbus(void __iomem *tbu_base,
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void __iomem *tcu_base, u32 testbus_version,
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int tbu_testbus)
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{
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u32 reg;
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reg = arm_smmu_debug_tbu_testbus_select(tbu_base, tcu_base,
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testbus_version, READ, 0);
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if (testbus_version == 1)
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reg = (reg & ~GENMASK(9, 0));
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else
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reg = (reg & ~GENMASK(7, 0));
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reg |= tbu_testbus;
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arm_smmu_debug_tbu_testbus_select(tbu_base, tcu_base,
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testbus_version, WRITE, reg);
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}
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void arm_smmu_debug_dump_tbu_testbus(struct device *dev, void __iomem *tbu_base,
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void __iomem *tcu_base, int tbu_testbus_sel,
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u32 testbus_version)
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{
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if (tbu_testbus_sel & TBU_CLK_GATE_CONTROLLER_TESTBUS_SEL) {
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dev_info(dev, "Dumping TBU clk gate controller:");
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arm_smmu_debug_program_tbu_testbus(tbu_base, tcu_base,
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testbus_version,
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TBU_CLK_GATE_CONTROLLER_TESTBUS);
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dev_info(dev, "testbus_sel: 0x%lx val: 0x%llx\n",
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arm_smmu_debug_tbu_testbus_select(tbu_base, tcu_base,
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testbus_version, READ, 0),
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arm_smmu_debug_tbu_testbus_output(tbu_base,
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testbus_version));
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}
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if (tbu_testbus_sel & TBU_QNS4_A2Q_TESTBUS_SEL) {
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dev_info(dev, "Dumping TBU qns4 a2q test bus");
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arm_smmu_debug_program_tbu_testbus(tbu_base, tcu_base,
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testbus_version, TBU_QNS4_A2Q_TESTBUS);
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arm_smmu_debug_dump_tbu_qns4_testbus(dev, tbu_base,
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tcu_base, testbus_version);
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}
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if (tbu_testbus_sel & TBU_QNS4_Q2A_TESTBUS_SEL) {
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dev_info(dev, "Dumping qns4 q2a test bus");
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arm_smmu_debug_program_tbu_testbus(tbu_base, tcu_base,
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testbus_version, TBU_QNS4_Q2A_TESTBUS);
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arm_smmu_debug_dump_tbu_qns4_testbus(dev, tbu_base,
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tcu_base, testbus_version);
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}
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if (tbu_testbus_sel & TBU_MULTIMASTER_QCHANNEL_TESTBUS_SEL) {
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dev_info(dev, "Dumping multi master qchannel:");
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arm_smmu_debug_program_tbu_testbus(tbu_base, tcu_base,
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testbus_version,
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TBU_MULTIMASTER_QCHANNEL_TESTBUS);
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dev_info(dev, "testbus_sel: 0x%x val: 0x%x\n",
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arm_smmu_debug_tbu_testbus_select(tbu_base,
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tcu_base, testbus_version, READ, 0),
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arm_smmu_debug_tbu_testbus_output(tbu_base,
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testbus_version));
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}
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}
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static void arm_smmu_debug_program_tcu_testbus(struct device *dev,
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void __iomem *base, void __iomem *tcu_base,
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unsigned long mask, int start, int end, int shift,
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bool print)
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{
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u32 reg;
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int i;
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for (i = start; i < end; i++) {
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reg = arm_smmu_debug_tcu_testbus_select(base, tcu_base,
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PTW_AND_CACHE_TESTBUS, READ, 0);
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reg &= mask;
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reg |= i << shift;
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arm_smmu_debug_tcu_testbus_select(base, tcu_base,
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PTW_AND_CACHE_TESTBUS, WRITE, reg);
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if (print)
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dev_info(dev, "testbus_sel: 0x%x Index: %d val: 0x%x\n",
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arm_smmu_debug_tcu_testbus_select(base,
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tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0),
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i, arm_smmu_debug_tcu_testbus_output(base));
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}
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}
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void arm_smmu_debug_dump_tcu_testbus(struct device *dev, void __iomem *base,
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void __iomem *tcu_base, int tcu_testbus_sel)
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{
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int i;
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if (tcu_testbus_sel & TCU_CACHE_TESTBUS_SEL) {
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dev_info(dev, "Dumping TCU cache testbus:\n");
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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TCU_CACHE_TESTBUS, 0, 1, 0, false);
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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~GENMASK(7, 0), 0, TCU_CACHE_LOOKUP_QUEUE_SIZE,
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2, true);
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}
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if (tcu_testbus_sel & TCU_PTW_TESTBUS_SEL) {
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dev_info(dev, "Dumping TCU PTW test bus:\n");
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base, 1,
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TCU_PTW_TESTBUS, TCU_PTW_TESTBUS + 1, 0, false);
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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~GENMASK(7, 2), 0, TCU_PTW_INTERNAL_STATES,
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2, true);
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for (i = TCU_PTW_QUEUE_START;
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i < TCU_PTW_QUEUE_START + TCU_PTW_QUEUE_SIZE; ++i) {
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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~GENMASK(7, 0), i, i + 1, 2, true);
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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~GENMASK(1, 0), TCU_PTW_TESTBUS_SEL2,
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TCU_PTW_TESTBUS_SEL2 + 1, 0, false);
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dev_info(dev, "testbus_sel: 0x%x Index: %d val: 0x%x\n",
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arm_smmu_debug_tcu_testbus_select(base,
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tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0),
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i, arm_smmu_debug_tcu_testbus_output(base));
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}
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}
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/* program ARM_SMMU_TESTBUS_SEL_HLOS1_NS to select TCU clk testbus*/
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arm_smmu_debug_tcu_testbus_select(base, tcu_base,
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CLK_TESTBUS, WRITE, TCU_CLK_TESTBUS_SEL);
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dev_info(dev, "Programming Tcu clk gate controller: testbus_sel: 0x%lx\n",
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arm_smmu_debug_tcu_testbus_select(base, tcu_base,
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CLK_TESTBUS, READ, 0));
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}
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void arm_smmu_debug_set_tnx_tcr_cntl(void __iomem *tbu_base, u64 val)
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{
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writel_relaxed(val, tbu_base + ARM_SMMU_TNX_TCR_CNTL);
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}
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unsigned long arm_smmu_debug_get_tnx_tcr_cntl(void __iomem *tbu_base)
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{
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return readl_relaxed(tbu_base + ARM_SMMU_TNX_TCR_CNTL);
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}
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void arm_smmu_debug_set_mask_and_match(void __iomem *tbu_base, u64 sel,
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u64 mask, u64 match)
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{
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writeq_relaxed(mask, tbu_base + ARM_SMMU_CAPTURE1_MASK(sel));
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writeq_relaxed(match, tbu_base + ARM_SMMU_CAPTURE1_MATCH(sel));
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}
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void arm_smmu_debug_get_mask_and_match(void __iomem *tbu_base, u64 *mask,
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u64 *match)
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{
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int i;
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for (i = 0; i < NO_OF_MASK_AND_MATCH; ++i) {
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mask[i] = readq_relaxed(tbu_base +
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ARM_SMMU_CAPTURE1_MASK(i+1));
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match[i] = readq_relaxed(tbu_base +
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ARM_SMMU_CAPTURE1_MATCH(i+1));
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}
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}
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void arm_smmu_debug_get_capture_snapshot(void __iomem *tbu_base,
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u64 snapshot[NO_OF_CAPTURE_POINTS][REGS_PER_CAPTURE_POINT])
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{
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int valid, i, j;
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valid = readl_relaxed(tbu_base + APPS_SMMU_TNX_TCR_CNTL_2);
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for (i = 0; i < NO_OF_CAPTURE_POINTS ; ++i) {
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if (valid & (1 << i))
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for (j = 0; j < REGS_PER_CAPTURE_POINT; ++j)
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snapshot[i][j] = readq_relaxed(tbu_base +
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ARM_SMMU_CAPTURE_SNAPSHOT(i, j));
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else
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for (j = 0; j < REGS_PER_CAPTURE_POINT; ++j)
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snapshot[i][j] = 0xdededede;
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}
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}
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void arm_smmu_debug_clear_intr_and_validbits(void __iomem *tbu_base)
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{
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int val = 0;
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val |= INTR_CLR;
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val |= RESET_VALID;
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writel_relaxed(val, tbu_base + ARM_SMMU_TNX_TCR_CNTL);
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}
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