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70 lines
2.3 KiB
70 lines
2.3 KiB
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __KGSL_RGMU_H
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#define __KGSL_RGMU_H
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#define RGMU_AO_IRQ_FENCE_ERR BIT(3)
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#define RGMU_AO_IRQ_MASK RGMU_AO_IRQ_FENCE_ERR
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#define RGMU_OOB_IRQ_ERR_MSG BIT(24)
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#define RGMU_OOB_IRQ_ACK_MASK GENMASK(23, 16)
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#define RGMU_OOB_IRQ_ERR_MSG_MASK GENMASK(31, 24)
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#define RGMU_OOB_IRQ_MASK RGMU_OOB_IRQ_ERR_MSG_MASK
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#define MAX_RGMU_CLKS 8
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/**
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* struct rgmu_device - rGMU device structure
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* @ver: RGMU firmware version
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* @reg_phys: RGMU CSR physical address
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* @reg_virt: RGMU CSR virtual address
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* @reg_len: RGMU CSR range
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* @rgmu_interrupt_num: RGMU interrupt number
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* @oob_interrupt_num: number of RGMU asserted OOB interrupt
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* @cx_gdsc: CX headswitch that controls power of RGMU and
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subsystem peripherals
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* @clks: RGMU clocks including the GPU
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* @gpu_clk: Pointer to GPU core clock
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* @rgmu_clk: Pointer to rgmu clock
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* @gpu_freqs: GPU frequency table with lowest freq at index 0
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* @num_gpupwrlevels: number GPU frequencies in GPU freq table
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* @flags: RGMU flags
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* @idle_level: Minimal GPU idle power level
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* @fault_count: RGMU fault count
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* @fw_image: RGMU firmware image
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*/
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struct rgmu_device {
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u32 ver;
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struct platform_device *pdev;
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unsigned long reg_phys;
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unsigned int reg_len;
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unsigned int rgmu_interrupt_num;
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unsigned int oob_interrupt_num;
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struct regulator *cx_gdsc;
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struct regulator *gx_gdsc;
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struct clk *clks[MAX_RGMU_CLKS];
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struct clk *gpu_clk;
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struct clk *rgmu_clk;
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unsigned int gpu_freqs[MAX_GX_LEVELS];
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unsigned int num_gpupwrlevels;
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unsigned int idle_level;
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unsigned int fault_count;
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const struct firmware *fw_image;
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};
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extern struct gmu_dev_ops adreno_a6xx_rgmudev;
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#define KGSL_RGMU_DEVICE(_a) ((struct rgmu_device *)((_a)->gmu_core.ptr))
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irqreturn_t rgmu_irq_handler(int irq, void *data);
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irqreturn_t oob_irq_handler(int irq, void *data);
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#endif /* __KGSL_RGMU_H */
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